add solutions

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tester_entity.vhg

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+-- VHDL Entity DigitalToAnalogConverter_test.DAC_tester.interface
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:43:18 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+ENTITY DAC_tester IS
+    GENERIC( 
+        signalBitNb    : positive := 16;
+        clockFrequency : real     := 60.0E6
+    );
+    PORT( 
+        lowpassOut : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        serialOut  : IN     std_ulogic;
+        clock      : OUT    std_ulogic;
+        parallelIn : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        reset      : OUT    std_ulogic
+    );
+
+-- Declarations
+
+END DAC_tester ;
+