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This commit is contained in:
Rémi Heredero
2024-03-15 15:03:34 +01:00
parent 3095603e39
commit 9ceb15c0ff
612 changed files with 272868 additions and 0 deletions
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38
zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/DAC_tester_test.vhd Normal file
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library ieee;
use ieee.math_real.all;
ARCHITECTURE test OF DAC_tester IS
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
signal sineFrequency: real := 20.0E3;
signal tReal: real := 0.0;
signal outAmplitude: real := 1.0;
signal outReal: real := 0.0;
signal outUnsigned: unsigned(parallelIn'range);
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
reset <= '1', '0' after 2*clockPeriod;
------------------------------------------------------------------------------
-- time signals
process(sClock)
begin
if rising_edge(sClock) then
tReal <= tReal + 1.0/clockFrequency;
end if;
end process;
outReal <= outAmplitude * ( sin(2.0*math_pi*sineFrequency*tReal) + 1.0) / 2.0;
outUnsigned <= to_unsigned(integer(outReal * real(2**(outUnsigned'length)-1)), outUnsigned'length);
parallelIn <= outUnsigned;
-- parallelIn <= shift_left(to_unsigned(1, parallelIn'length), parallelIn'length-1);
-- parallelIn <= shift_left(to_unsigned(3, parallelIn'length), parallelIn'length-2);
END ARCHITECTURE test;

15
zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_entity.vhg Normal file
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-- VHDL Entity DigitalToAnalogConverter_test.DAC_tb.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:05:57 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY DAC_tb IS
-- Declarations
END DAC_tb ;

122
zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_struct.vhg Normal file
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--
-- VHDL Architecture DigitalToAnalogConverter_test.DAC_tb.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:43:18 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
LIBRARY DigitalToAnalogConverter;
LIBRARY DigitalToAnalogConverter_test;
LIBRARY WaveformGenerator;
ARCHITECTURE struct OF DAC_tb IS
-- Architecture declarations
constant signalBitNb: positive := 16;
constant lowpassShiftBitNb: positive := 8;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL clock : std_ulogic;
SIGNAL lowpassIn : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL lowpassOut : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL parallelIn : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL reset : std_ulogic;
SIGNAL serialOut : std_ulogic;
-- Component Declarations
COMPONENT DAC
GENERIC (
signalBitNb : positive := 16
);
PORT (
serialOut : OUT std_ulogic ;
parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic
);
END COMPONENT;
COMPONENT DAC_tester
GENERIC (
signalBitNb : positive := 16;
clockFrequency : real := 60.0E6
);
PORT (
lowpassOut : IN unsigned (signalBitNb-1 DOWNTO 0);
serialOut : IN std_ulogic ;
clock : OUT std_ulogic ;
parallelIn : OUT unsigned (signalBitNb-1 DOWNTO 0);
reset : OUT std_ulogic
);
END COMPONENT;
COMPONENT lowpass
GENERIC (
signalBitNb : positive := 16;
shiftBitNb : positive := 12
);
PORT (
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic ;
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
FOR ALL : DAC_tester USE ENTITY DigitalToAnalogConverter_test.DAC_tester;
FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
LowpassIn <= (others => serialOut);
-- Instance port mappings.
I_DUT : DAC
GENERIC MAP (
signalBitNb => signalBitNb
)
PORT MAP (
serialOut => serialOut,
parallelIn => parallelIn,
clock => clock,
reset => reset
);
I_tester : DAC_tester
GENERIC MAP (
signalBitNb => signalBitNb,
clockFrequency => clockFrequency
)
PORT MAP (
lowpassOut => lowpassOut,
serialOut => serialOut,
clock => clock,
parallelIn => parallelIn,
reset => reset
);
I_filt : lowpass
GENERIC MAP (
signalBitNb => signalBitNb,
shiftBitNb => lowpassShiftBitNb
)
PORT MAP (
lowpassOut => lowpassOut,
clock => clock,
reset => reset,
lowpassIn => lowpassIn
);
END struct;

29
zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tester_entity.vhg Normal file
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-- VHDL Entity DigitalToAnalogConverter_test.DAC_tester.interface
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:43:18 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY DAC_tester IS
GENERIC(
signalBitNb : positive := 16;
clockFrequency : real := 60.0E6
);
PORT(
lowpassOut : IN unsigned (signalBitNb-1 DOWNTO 0);
serialOut : IN std_ulogic;
clock : OUT std_ulogic;
parallelIn : OUT unsigned (signalBitNb-1 DOWNTO 0);
reset : OUT std_ulogic
);
-- Declarations
END DAC_tester ;