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--
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-- VHDL Architecture SplineInterpolator.sineGen.struct
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 14:42:04 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY SplineInterpolator;
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LIBRARY WaveformGenerator;
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ARCHITECTURE struct OF sineGen IS
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-- Architecture declarations
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constant tableAddressBitNb : positive := 3;
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constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb;
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constant coeffBitNb : positive := signalBitNb+4;
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-- Internal signal declarations
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SIGNAL a : signed(coeffBitNb-1 DOWNTO 0);
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SIGNAL b : signed(coeffBitNb-1 DOWNTO 0);
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SIGNAL c : signed(coeffBitNb-1 DOWNTO 0);
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SIGNAL d : signed(coeffBitNb-1 DOWNTO 0);
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SIGNAL logic0 : std_ulogic;
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SIGNAL logic1 : std_ulogic;
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SIGNAL newPolynom : std_ulogic;
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SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0);
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SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0);
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SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0);
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SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0);
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SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0);
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SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0);
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SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0);
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-- Implicit buffer signal declarations
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SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0);
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-- Component Declarations
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COMPONENT interpolatorCalculatePolynom
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GENERIC (
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signalBitNb : positive := 16;
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coeffBitNb : positive := 16;
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oversamplingBitNb : positive := 8
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);
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PORT (
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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restartPolynom : IN std_ulogic ;
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d : IN signed (coeffBitNb-1 DOWNTO 0);
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sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
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c : IN signed (coeffBitNb-1 DOWNTO 0);
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b : IN signed (coeffBitNb-1 DOWNTO 0);
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a : IN signed (coeffBitNb-1 DOWNTO 0);
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en : IN std_ulogic
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);
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END COMPONENT;
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COMPONENT interpolatorCoefficients
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GENERIC (
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bitNb : positive := 16;
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coeffBitNb : positive := 16
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);
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PORT (
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sample1 : IN signed (bitNb-1 DOWNTO 0);
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sample2 : IN signed (bitNb-1 DOWNTO 0);
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sample3 : IN signed (bitNb-1 DOWNTO 0);
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sample4 : IN signed (bitNb-1 DOWNTO 0);
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a : OUT signed (coeffBitNb-1 DOWNTO 0);
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b : OUT signed (coeffBitNb-1 DOWNTO 0);
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c : OUT signed (coeffBitNb-1 DOWNTO 0);
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d : OUT signed (coeffBitNb-1 DOWNTO 0);
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interpolateLinear : IN std_ulogic
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);
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END COMPONENT;
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COMPONENT interpolatorShiftRegister
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GENERIC (
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signalBitNb : positive := 16
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);
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PORT (
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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shiftSamples : IN std_ulogic ;
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sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
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sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT interpolatorTrigger
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GENERIC (
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counterBitNb : positive := 4
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);
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PORT (
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triggerOut : OUT std_ulogic ;
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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en : IN std_ulogic
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);
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END COMPONENT;
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COMPONENT offsetToUnsigned
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GENERIC (
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bitNb : positive := 16
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);
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PORT (
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unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
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signedIn : IN signed (bitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT resizer
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GENERIC (
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inputBitNb : positive := 16;
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outputBitNb : positive := 16
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);
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PORT (
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resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
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resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT sineTable
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GENERIC (
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inputBitNb : positive := 16;
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outputBitNb : positive := 16;
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tableAddressBitNb : positive := 3
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);
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PORT (
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sine : OUT signed (outputBitNb-1 DOWNTO 0);
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phase : IN unsigned (inputBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT sawtoothGen
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GENERIC (
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bitNb : positive := 16
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);
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PORT (
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sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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step : IN unsigned (bitNb-1 DOWNTO 0);
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en : IN std_ulogic
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);
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END COMPONENT;
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COMPONENT sawtoothToSquare
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GENERIC (
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bitNb : positive := 16
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);
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PORT (
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square : OUT unsigned (bitNb-1 DOWNTO 0);
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sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT sawtoothToTriangle
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GENERIC (
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bitNb : positive := 16
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);
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PORT (
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triangle : OUT unsigned (bitNb-1 DOWNTO 0);
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sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom;
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FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients;
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FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister;
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FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger;
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FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned;
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FOR ALL : resizer USE ENTITY SplineInterpolator.resizer;
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FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
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FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
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FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
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FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 2 eb2
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logic1 <= '1';
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-- HDL Embedded Text Block 3 eb3
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logic0 <= '0';
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-- Instance port mappings.
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I_spline : interpolatorCalculatePolynom
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GENERIC MAP (
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signalBitNb => signalBitNb,
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coeffBitNb => coeffBitNb,
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oversamplingBitNb => sampleCountBitNb
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)
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PORT MAP (
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clock => clock,
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reset => reset,
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restartPolynom => newPolynom,
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d => d,
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sampleOut => sineSigned,
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c => c,
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b => b,
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a => a,
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en => logic1
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);
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I_coeffs : interpolatorCoefficients
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GENERIC MAP (
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bitNb => signalBitNb,
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coeffBitNb => coeffBitNb
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)
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PORT MAP (
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sample1 => sample1,
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sample2 => sample2,
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sample3 => sample3,
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sample4 => sample4,
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a => a,
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b => b,
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c => c,
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d => d,
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interpolateLinear => logic0
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);
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I_shReg : interpolatorShiftRegister
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GENERIC MAP (
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signalBitNb => signalBitNb
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)
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PORT MAP (
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clock => clock,
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reset => reset,
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shiftSamples => newPolynom,
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sampleIn => sineSamples,
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sample1 => sample1,
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sample2 => sample2,
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sample3 => sample3,
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sample4 => sample4
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);
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I_trig : interpolatorTrigger
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GENERIC MAP (
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counterBitNb => sampleCountBitNb
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)
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PORT MAP (
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triggerOut => newPolynom,
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clock => clock,
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reset => reset,
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en => logic1
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);
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I_unsigned : offsetToUnsigned
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GENERIC MAP (
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bitNb => signalBitNb
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)
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PORT MAP (
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unsignedOut => sine,
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signedIn => sineSigned
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);
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I_size : resizer
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GENERIC MAP (
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inputBitNb => phaseBitNb,
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outputBitNb => signalBitNb
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)
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PORT MAP (
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resizeOut => sawtooth_internal,
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resizeIn => phase
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);
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I_sin : sineTable
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GENERIC MAP (
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inputBitNb => phaseBitNb,
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outputBitNb => signalBitNb,
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tableAddressBitNb => tableAddressBitNb
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)
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PORT MAP (
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sine => sineSamples,
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phase => phase
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);
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I_saw : sawtoothGen
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GENERIC MAP (
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bitNb => phaseBitNb
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)
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PORT MAP (
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sawtooth => phase,
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clock => clock,
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reset => reset,
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step => step,
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en => logic1
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);
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I_square : sawtoothToSquare
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GENERIC MAP (
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bitNb => signalBitNb
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)
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PORT MAP (
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square => square,
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sawtooth => sawtooth_internal
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);
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I_tri : sawtoothToTriangle
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GENERIC MAP (
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bitNb => signalBitNb
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)
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PORT MAP (
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triangle => triangle,
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sawtooth => sawtooth_internal
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);
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-- Implicit buffered output assignments
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sawtooth <= sawtooth_internal;
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END struct;
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