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This commit is contained in:
Rémi Heredero
2024-03-15 15:03:34 +01:00
parent 3095603e39
commit 9ceb15c0ff
612 changed files with 272868 additions and 0 deletions
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22
zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformGen_tester_test.vhd Normal file
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ARCHITECTURE test OF waveformGen_tester IS
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
begin
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
reset <= '1', '0' after 2*clockPeriod;
------------------------------------------------------------------------------
-- enable
en <= '0', '1' after 100 us;
------------------------------------------------------------------------------
-- frequency control
step <= to_unsigned(2**(step'length-13), step'length);
END ARCHITECTURE test;

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_entity.vhg Normal file
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-- VHDL Entity WaveformGenerator_test.waveformGen_tb.symbol
--
-- Created:
-- by - francois.corthay.UNKNOWN (WEA30906)
-- at - 14:48:16 25.02.2019
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY waveformGen_tb IS
-- Declarations
END waveformGen_tb ;

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg Normal file
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--
-- VHDL Architecture WaveformGenerator_test.waveformGen_tb.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:39:46 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
LIBRARY WaveformGenerator;
LIBRARY WaveformGenerator_test;
ARCHITECTURE struct OF waveformGen_tb IS
-- Architecture declarations
constant bitNb: positive := 16;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL clock : std_ulogic;
SIGNAL en : std_ulogic;
SIGNAL reset : std_ulogic;
SIGNAL step : unsigned(bitNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT waveformGen
GENERIC (
phaseBitNb : positive := 16;
signalBitNb : positive := 16
);
PORT (
clock : IN std_ulogic ;
en : IN std_ulogic ;
reset : IN std_ulogic ;
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
polygon : OUT unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : OUT unsigned (phaseBitNb-1 DOWNTO 0);
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT waveformGen_tester
GENERIC (
bitNb : positive := 16;
clockFrequency : real := 60.0E6
);
PORT (
clock : OUT std_ulogic ;
en : OUT std_ulogic ;
reset : OUT std_ulogic ;
step : OUT unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : waveformGen USE ENTITY WaveformGenerator.waveformGen;
FOR ALL : waveformGen_tester USE ENTITY WaveformGenerator_test.waveformGen_tester;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I_DUT : waveformGen
GENERIC MAP (
phaseBitNb => bitNb,
signalBitNb => bitNb
)
PORT MAP (
clock => clock,
en => en,
reset => reset,
step => step,
polygon => OPEN,
sawtooth => OPEN,
sine => OPEN,
square => OPEN,
triangle => OPEN
);
I_tb : waveformGen_tester
GENERIC MAP (
bitNb => bitNb,
clockFrequency => clockFrequency
)
PORT MAP (
clock => clock,
en => en,
reset => reset,
step => step
);
END struct;

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg Normal file
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-- VHDL Entity WaveformGenerator_test.waveformGen_tester.interface
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:39:31 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY waveformGen_tester IS
GENERIC(
bitNb : positive := 16;
clockFrequency : real := 60.0E6
);
PORT(
clock : OUT std_ulogic;
en : OUT std_ulogic;
reset : OUT std_ulogic;
step : OUT unsigned (bitNb-1 DOWNTO 0)
);
-- Declarations
END waveformGen_tester ;

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.cache.dat Normal file
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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformGen_tester_test.vhd._fpf Normal file
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DIALECT atom VHDL_2008

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhd._fpf Normal file
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DIALECT atom VHDL_2008

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

1
zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhd._fpf Normal file
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DIALECT atom VHDL_2008

1
zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhd._fpf Normal file
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DIALECT atom VHDL_2008

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_entity.xrf Normal file
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DESIGN waveform@gen_tb
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN waveform@gen_tb
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN waveform@gen_tb
VIEW symbol.sb
GRAPHIC 1,0 11 0
DESIGN waveform@gen_tb
VIEW symbol.sb
GRAPHIC 1,0 12 0

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf Normal file
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DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 142,0 9 0
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 12
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 0,0 16 2
DESIGN waveform@gen_tb
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GRAPHIC 1,0 19 0
DESIGN waveform@gen_tb
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DESIGN waveform@gen_tb
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DESIGN waveform@gen_tb
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VIEW struct.bd
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DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 28
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 29
LIBRARY WaveformGenerator
DESIGN waveform@gen
VIEW struct
GRAPHIC 954,0 31 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 14,0 32 1
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 52,0 37 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 123,0 38 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 88,0 39 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 113,0 40 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 93,0 41 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 98,0 42 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 103,0 43 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 108,0 44 0
DESIGN waveform@gen
VIEW symbol.sb
GRAPHIC 118,0 45 0
LIBRARY WaveformGenerator_test
DESIGN waveform@gen_tester
VIEW test
GRAPHIC 421,0 48 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 14,0 49 1
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 55,0 54 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 702,0 55 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 47,0 56 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 596,0 57 0
LIBRARY WaveformGenerator_test
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 60
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 954,0 63 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 421,0 64 0
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 67
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 69
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 954,0 71 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 961,0 72 1
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 55,0 77 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 702,0 78 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 47,0 79 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 596,0 80 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 421,0 87 0
DESIGN waveform@gen_tb
VIEW struct.bd
GRAPHIC 428,0 88 1
DESIGN waveform@gen_tb
VIEW struct.bd
NO_GRAPHIC 99

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf Normal file
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DESIGN waveform@gen_tester
VIEW interface
NO_GRAPHIC 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 18,0 8 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 13,0 13 1
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 636,0 18 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 641,0 19 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 646,0 20 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 651,0 21 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1,0 24 0
DESIGN waveform@gen_tester
VIEW interface
GRAPHIC 1,0 25 0

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tb._epf Normal file
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DEFAULT_FILE atom waveform@gen_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tester._epf Normal file
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DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom waveformGen_tester_test.vhd

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.lck Normal file
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EDIT_LOCK
andrea.guerrier
UNKNOWN
VS-W60518
22468
18.01.2024-14:00:35.771000

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zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tester/interface Normal file
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