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This commit is contained in:
Rémi Heredero
2024-03-15 15:03:34 +01:00
parent 3095603e39
commit 9ceb15c0ff
612 changed files with 272868 additions and 0 deletions
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28
zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_entity.vhg Normal file
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-- VHDL Entity WaveformGenerator.lowpass.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY lowpass IS
GENERIC(
signalBitNb : positive := 16;
shiftBitNb : positive := 12
);
PORT(
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
clock : IN std_ulogic;
reset : IN std_ulogic;
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
);
-- Declarations
END lowpass ;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_masterVersion.vhd Normal file
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ARCHITECTURE masterVersion OF lowpass IS
constant additionalBitNb: positive := shiftBitNb;
signal lowpassReg: unsigned(lowpassIn'length+additionalBitNb-1 downto 0);
begin
filter: process(reset, clock)
begin
if reset = '1' then
lowpassReg <= (others => '0');
elsif rising_edge(clock) then
lowpassReg <= lowpassReg + lowpassIn - shift_right(lowpassReg, shiftBitNb);
end if;
end process filter;
lowpassOut <= lowpassReg(lowpassReg'high downto lowpassReg'high-lowpassOut'length+1);
END ARCHITECTURE masterVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF lowpass IS
BEGIN
lowpassOut <= (others => '0');
END ARCHITECTURE studentVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_masterVersion.vhd Normal file
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ARCHITECTURE masterVersion OF sawtoothGen IS
signal counter: unsigned(sawtooth'range);
begin
count: process(reset, clock)
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clock) then
if en = '1' then
counter <= counter + step;
end if;
end if;
end process count;
sawtooth <= counter;
END ARCHITECTURE masterVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF sawtoothGen IS
BEGIN
sawtooth <= (others => '0');
END ARCHITECTURE studentVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_masterVersion.vhd Normal file
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ARCHITECTURE masterVersion OF sawtoothToSquare IS
BEGIN
square <= (others => sawtooth(sawtooth'high));
END ARCHITECTURE masterVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF sawtoothToSquare IS
BEGIN
square <= (others => '0');
END ARCHITECTURE studentVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_masterVersion.vhd Normal file
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ARCHITECTURE masterVersion OF sawtoothToTriangle IS
signal MSB: std_uLogic;
signal triangleInt: unsigned(triangle'range);
begin
MSB <= sawtooth(sawtooth'high);
foldDown: process(MSB, sawtooth)
begin
if MSB = '0' then
triangleInt <= sawtooth;
else
triangleInt <= not sawtooth;
end if;
end process foldDown;
triangle <= triangleInt(triangleInt'high-1 downto 0) & '0';
END ARCHITECTURE masterVersion;

4
zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF sawtoothToTriangle IS
BEGIN
triangle <= (others => '0');
END ARCHITECTURE studentVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothgen_entity.vhg Normal file
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-- VHDL Entity WaveformGenerator.sawtoothGen.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sawtoothGen IS
GENERIC(
bitNb : positive := 16
);
PORT(
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
clock : IN std_ulogic;
reset : IN std_ulogic;
step : IN unsigned (bitNb-1 DOWNTO 0);
en : IN std_ulogic
);
-- Declarations
END sawtoothGen ;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtosquare_entity.vhg Normal file
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-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sawtoothToSquare IS
GENERIC(
bitNb : positive := 16
);
PORT(
square : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
-- Declarations
END sawtoothToSquare ;

25
zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtotriangle_entity.vhg Normal file
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-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sawtoothToTriangle IS
GENERIC(
bitNb : positive := 16
);
PORT(
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
-- Declarations
END sawtoothToTriangle ;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_masterVersion.vhd Normal file
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ARCHITECTURE masterVersion OF triangleToPolygon IS
constant clipLow: positive := 2**(triangle'length-2);
constant clipHigh: positive := 5*clipLow;
signal triangleGain: unsigned(triangle'length downto 0);
begin
gain_1_5: process(triangle)
begin
triangleGain <= ("0" & triangle) + ( "00" & triangle(triangle'high downto 1) );
end process gain_1_5;
clip: process(triangleGain)
begin
if triangleGain < clipLow then
polygon <= (others => '0');
elsif triangleGain > clipHigh then
polygon <= (others => '1');
else
polygon <= triangleGain(polygon'range) - clipLow;
end if;
end process clip;
END ARCHITECTURE masterVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF triangleToPolygon IS
BEGIN
polygon <= (others => '0');
END ARCHITECTURE studentVersion;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangletopolygon_entity.vhg Normal file
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-- VHDL Entity WaveformGenerator.triangleToPolygon.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:02:49 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY triangleToPolygon IS
GENERIC(
bitNb : positive := 16
);
PORT(
polygon : OUT unsigned (bitNb-1 DOWNTO 0);
triangle : IN unsigned (bitNb-1 DOWNTO 0)
);
-- Declarations
END triangleToPolygon ;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_entity.vhg Normal file
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-- VHDL Entity WaveformGenerator.waveformGen.symbol
--
-- Created:
-- by - francois.corthay.UNKNOWN (WEA20303)
-- at - 17:19:13 06.03.2019
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY waveformGen IS
GENERIC(
phaseBitNb : positive := 16;
signalBitNb : positive := 16
);
PORT(
clock : IN std_ulogic;
en : IN std_ulogic;
reset : IN std_ulogic;
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
polygon : OUT unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : OUT unsigned (phaseBitNb-1 DOWNTO 0);
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
);
-- Declarations
END waveformGen ;

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zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_struct.vhg Normal file
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--
-- VHDL Architecture WaveformGenerator.waveformGen.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:40:08 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY WaveformGenerator;
ARCHITECTURE struct OF waveformGen IS
-- Architecture declarations
-- Internal signal declarations
-- Implicit buffer signal declarations
SIGNAL polygon_internal : unsigned (signalBitNb-1 DOWNTO 0);
SIGNAL sawtooth_internal : unsigned (phaseBitNb-1 DOWNTO 0);
SIGNAL triangle_internal : unsigned (signalBitNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT lowpass
GENERIC (
signalBitNb : positive := 16;
shiftBitNb : positive := 12
);
PORT (
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic ;
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sawtoothGen
GENERIC (
bitNb : positive := 16
);
PORT (
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic ;
step : IN unsigned (bitNb-1 DOWNTO 0);
en : IN std_ulogic
);
END COMPONENT;
COMPONENT sawtoothToSquare
GENERIC (
bitNb : positive := 16
);
PORT (
square : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sawtoothToTriangle
GENERIC (
bitNb : positive := 16
);
PORT (
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT triangleToPolygon
GENERIC (
bitNb : positive := 16
);
PORT (
polygon : OUT unsigned (bitNb-1 DOWNTO 0);
triangle : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
FOR ALL : triangleToPolygon USE ENTITY WaveformGenerator.triangleToPolygon;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I_lp : lowpass
GENERIC MAP (
signalBitNb => signalBitNb,
shiftBitNb => 10
)
PORT MAP (
lowpassOut => sine,
clock => clock,
reset => reset,
lowpassIn => polygon_internal
);
I_saw : sawtoothGen
GENERIC MAP (
bitNb => phaseBitNb
)
PORT MAP (
sawtooth => sawtooth_internal,
clock => clock,
reset => reset,
step => step,
en => en
);
I_square : sawtoothToSquare
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
square => square,
sawtooth => sawtooth_internal
);
I_tri : sawtoothToTriangle
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
triangle => triangle_internal,
sawtooth => sawtooth_internal
);
I_poly : triangleToPolygon
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
polygon => polygon_internal,
triangle => triangle_internal
);
-- Implicit buffered output assignments
polygon <= polygon_internal;
sawtooth <= sawtooth_internal;
triangle <= triangle_internal;
END struct;