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Rémi Heredero
2024-03-15 15:03:34 +01:00
parent 3095603e39
commit 9ceb15c0ff
612 changed files with 272868 additions and 0 deletions
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64
zz-solutions/01-WaveformGenerator/Prefs/dp_user/v2_72/dp_user_prefs Normal file
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[LexParser]
[Editor]
recentFile0=/usr/opt/HDS/hdl_libs/ieee/hdl/std_logic_1164.vhdl
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mark.lineImage=blueball
[Printer]
ENSCRIPT_LIBRARY=/usr/opt/HDS/resources/enscript/share/enscript
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geom0Group2=top H
geom0Group3=top H
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state0Bookmarks=1
state0Windows=1
state0DocumentTools=1
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signalRefuseDropBg=red
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[Browser]
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normalTextFg=black
[Replace]
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19
zz-solutions/01-WaveformGenerator/Prefs/hds.hdp Normal file
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[Concat]
[ModelSim]
WaveformGenerator = $SCRATCH_DIR/WaveformGenerator
WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test
[hdl]
ieee = $HDS_HOME/hdl_libs/ieee/hdl
std = $HDS_HOME/hdl_libs/std/hdl
WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hdl
WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hdl
[hds]
ieee = $HDS_HOME/hdl_libs/ieee/hds
std = $HDS_HOME/hdl_libs/std/hds
WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hds
WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hds
[library_type]
ieee = standard
std = standard
[shared]
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23
zz-solutions/01-WaveformGenerator/Prefs/hds_team/shared.hdp Normal file
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std = $HDS_HOME/hdl_libs/std/hds
synopsys = $HDS_HOME/hdl_libs/synopsys/hds
verilog = $HDS_HOME/hdl_libs/verilog/hds
vital2000 = $HDS_HOME/hdl_libs/vital2000/hds
[hdl]
ieee = $HDS_HOME/hdl_libs/ieee/hdl
std = $HDS_HOME/hdl_libs/std/hdl
synopsys = $HDS_HOME/hdl_libs/synopsys/hdl
verilog = $HDS_HOME/hdl_libs/verilog/hdl
vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl
[library_type]
ieee = standard
std = standard
synopsys = standard
verilog = standard
vital2000 = standard

55
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs Normal file
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VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
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VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
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VMGeneratedHDL 0
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273
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl Normal file
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55
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs Normal file
View File

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version "8.0"
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fcDGProps [
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asmDGProps [
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syDGProps [
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)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
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55
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs.bak Normal file
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version "8.0"
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]
)
(VersionControlTeamPreferences
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VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
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VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
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VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
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273
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl Normal file
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55
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs Normal file
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version "8.0"
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273
zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl Normal file
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zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd Normal file
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zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk Normal file
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version "1.1"
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96
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk Normal file
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@@ -0,0 +1,96 @@
version "1.1"
HDSTool (HDSTool
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162
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk Normal file
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@@ -0,0 +1,162 @@
version "1.1"
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163
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk Normal file
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@@ -0,0 +1,163 @@
version "1.1"
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15
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd Normal file
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@@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd Normal file
View File

@@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd Normal file
View File

@@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd Normal file
View File

@@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
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%(entity)

16
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd Normal file
View File

@@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd Normal file
View File

@@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
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6800
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6800
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs.bak Normal file
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162
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk Normal file
View File

@@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
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41
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/generate.tsk Normal file
View File

@@ -0,0 +1,41 @@
version "1.1"
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98
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk Normal file
View File

@@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
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83
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk Normal file
View File

@@ -0,0 +1,83 @@
version "1.1"
HDSFlow (HDSFlow
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98
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk Normal file
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@@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
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bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"1"
"runMethod"
"gui"
"runnableObject"
"ModelSimSimulator"
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"tcl_plugin"
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"0"
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"TaskSetting"
(SettingsMap
settingsMap [
"Arguments"
""
"Arguments1"
"do controller.do"
"Arguments2"
"controller.do"
"Communication"
"1"
"DelaySelection"
"typ"
"GlitchGeneration"
"1"
"InitCmd"
"$SIMULATION_DIR/waveformGen.do"
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""
"RemoteHost"
""
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onPulldownMenu 0
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hierDepth 3
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162
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk Normal file
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@@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
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onShortcutBar 0
onPulldownMenu 0
onToolbar 1
enabled 1
hierDepth 1
subTasks [
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associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
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""
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TaskName "Concatenate HDL"
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"v"
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bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "comment out library declarations for singles file"
taskSettings [
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(SettingsMap
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163
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk Normal file
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@@ -0,0 +1,163 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
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(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
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hierDepth 1
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TaskName "Update.xise"
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hasBitmap 1
tooltip "Update file references in the Xilnx project .xise file"
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15
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd Normal file
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@@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd Normal file
View File

@@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd Normal file
View File

@@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd Normal file
View File

@@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd Normal file
View File

@@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd Normal file
View File

@@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);