add encoding SM --not finish yet

zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousgenerator_test_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity Lissajous_test.lissajousGenerator_test.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:07:27 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY lissajousGenerator_test IS
+-- Declarations
+
+END lissajousGenerator_test ;
+