add encoding SM --not finish yet

zz-solutions/04-Lissajous/Lissajous/hdl/lissajousgenerator_entity.vhg

@@ -0,0 +1,31 @@
+-- VHDL Entity Lissajous.lissajousGenerator.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:07:53 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY lissajousGenerator IS
+    GENERIC( 
+        signalBitNb : positive := 16;
+        phaseBitNb  : positive := 16;
+        stepX       : positive := 1;
+        stepY       : positive := 1
+    );
+    PORT( 
+        clock      : IN     std_ulogic;
+        reset      : IN     std_ulogic;
+        triggerOut : OUT    std_ulogic;
+        xOut       : OUT    std_ulogic;
+        yOut       : OUT    std_ulogic
+    );
+
+-- Declarations
+
+END lissajousGenerator ;
+