add encoding SM --not finish yet

zz-solutions/04-Lissajous/Board/hdl/inverterin_entity.vhg

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+-- VHDL Entity Board.inverterIn.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:07:14 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY inverterIn IS
+    PORT( 
+        in1  : IN     std_uLogic;
+        out1 : OUT    std_uLogic
+    );
+
+-- Declarations
+
+END inverterIn ;
+