add resize + tabel

01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs

@@ -6220,7 +6220,7 @@ yPos 0
 width 1936
 height 1056
 activeSidePanelTab 2
-activeLibraryTab 2
+activeLibraryTab 1
 sidePanelSize 278
 showUnixHiddenFiles 0
 componentBrowserXpos 569

01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs.bak

@@ -6220,7 +6220,7 @@ yPos 0
 width 1936
 height 1056
 activeSidePanelTab 2
-activeLibraryTab 2
+activeLibraryTab 1
 sidePanelSize 278
 showUnixHiddenFiles 0
 componentBrowserXpos 569

01-WaveformGenerator/WaveformGenerator/hdl/lowpass_entity.vhg

@@ -1,8 +1,8 @@
 -- VHDL Entity WaveformGenerator.lowpass.symbol
 --
 -- Created:
---          by - francois.francois (Aphelia)
+--          by - remi.heredero.UNKNOWN (WE2330808)
---          at - 08:02:49 03/11/19
+--          at - 15:16:08 01.03.2024
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
 --

01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_struct.vhg

@@ -2,8 +2,8 @@
 -- VHDL Architecture WaveformGenerator.waveformGen.struct
 --
 -- Created:
---          by - axel.amand.UNKNOWN (WE7860)
+--          by - remi.heredero.UNKNOWN (WE2330808)
---          at - 14:40:08 28.04.2023
+--          at - 15:15:34 01.03.2024
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
 --
@@ -29,7 +29,7 @@ ARCHITECTURE struct OF waveformGen IS
     COMPONENT lowpass
     GENERIC (
         signalBitNb : positive := 16;
-        shiftBitNb  : positive := 12
+        shiftBitNb  : positive := 6
     );
     PORT (
         lowpassOut : OUT    unsigned (signalBitNb-1 DOWNTO 0);

01-WaveformGenerator/WaveformGenerator/hds/lowpass/symbol.sb

@@ -16,8 +16,8 @@ libraryRefs [
 "ieee"
 ]
 )
-version "26.1"
+version "27.1"
-appVersion "2018.1 (Build 12)"
+appVersion "2019.2 (Build 5)"
 model (Symbol
 commonDM (CommonDM
 ldm (LogicalDM
@@ -118,17 +118,17 @@ sheetRow (SheetRow
 headerVa (MVa
 cellColor "49152,49152,49152"
 fontColor "0,0,0"
-font "courier,10,0"
+font "Tahoma,10,0"
 )
 cellVa (MVa
 cellColor "65535,65535,65535"
 fontColor "0,0,0"
-font "courier,10,0"
+font "Tahoma,10,0"
 )
 groupVa (MVa
 cellColor "39936,56832,65280"
 fontColor "0,0,0"
-font "courier,10,0"
+font "Tahoma,10,0"
 )
 emptyMRCItem *19 (MRCItem
 litem &1
@@ -186,7 +186,7 @@ sheetCol (SheetCol
 propVa (MVa
 cellColor "0,49152,49152"
 fontColor "0,0,0"
-font "courier,10,0"
+font "Tahoma,10,0"
 textAngle 90
 )
 uid 91,0
@@ -314,17 +314,17 @@ sheetRow (SheetRow
 headerVa (MVa
 cellColor "49152,49152,49152"
 fontColor "0,0,0"
-font "courier,10,0"
+font "Tahoma,10,0"
 )
 cellVa (MVa
 cellColor "65535,65535,65535"
 fontColor "0,0,0"
-font "courier,10,0"
+font "Tahoma,10,0"
 )
 groupVa (MVa
 cellColor "39936,56832,65280"
 fontColor "0,0,0"
-font "courier,10,0"
+font "Tahoma,10,0"
 )
 emptyMRCItem *50 (MRCItem
 litem &35
@@ -370,7 +370,7 @@ sheetCol (SheetCol
 propVa (MVa
 cellColor "0,49152,49152"
 fontColor "0,0,0"
-font "courier,10,0"
+font "Tahoma,10,0"
 textAngle 90
 )
 uid 122,0
@@ -439,23 +439,23 @@ value " "
 )
 (vvPair
 variable "HDLDir"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hdl"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb.info"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb.user"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
 )
 (vvPair
 variable "appl"
@@ -479,27 +479,27 @@ value "%(unit)_%(view)_config"
 )
 (vvPair
 variable "d"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass"
 )
 (vvPair
 variable "d_logical"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass"
 )
 (vvPair
 variable "date"
-value "03/11/19"
+value "01.03.2024"
 )
 (vvPair
 variable "day"
-value "Mon"
+value "ven."
 )
 (vvPair
 variable "day_long"
-value "Monday"
+value "vendredi"
 )
 (vvPair
 variable "dd"
-value "11"
+value "01"
 )
 (vvPair
 variable "designName"
@@ -527,31 +527,31 @@ value "symbol"
 )
 (vvPair
 variable "graphical_source_author"
-value "francois"
+value "remi.heredero"
 )
 (vvPair
 variable "graphical_source_date"
-value "03/11/19"
+value "01.03.2024"
 )
 (vvPair
 variable "graphical_source_group"
-value "francois"
+value "UNKNOWN"
 )
 (vvPair
 variable "graphical_source_host"
-value "Aphelia"
+value "WE2330808"
 )
 (vvPair
 variable "graphical_source_time"
-value "08:02:49"
+value "15:16:08"
 )
 (vvPair
 variable "group"
-value "francois"
+value "UNKNOWN"
 )
 (vvPair
 variable "host"
-value "Aphelia"
+value "WE2330808"
 )
 (vvPair
 variable "language"
@@ -587,19 +587,19 @@ value "lowpass"
 )
 (vvPair
 variable "month"
-value "Mar"
+value "mars"
 )
 (vvPair
 variable "month_long"
-value "March"
+value "mars"
 )
 (vvPair
 variable "p"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\lowpass\\symbol.sb"
 )
 (vvPair
 variable "package_name"
@@ -607,7 +607,7 @@ value "<Undefined Variable>"
 )
 (vvPair
 variable "project_name"
-value "waveformGenerator"
+value "hds"
 )
 (vvPair
 variable "series"
@@ -675,7 +675,7 @@ value "symbol"
 )
 (vvPair
 variable "time"
-value "08:02:49"
+value "15:16:08"
 )
 (vvPair
 variable "unit"
@@ -683,11 +683,11 @@ value "lowpass"
 )
 (vvPair
 variable "user"
-value "francois"
+value "remi.heredero"
 )
 (vvPair
 variable "version"
-value "2018.1 (Build 12)"
+value "2019.2 (Build 5)"
 )
 (vvPair
 variable "view"
@@ -695,11 +695,11 @@ value "symbol"
 )
 (vvPair
 variable "year"
-value "2019"
+value "2024"
 )
 (vvPair
 variable "yy"
-value "19"
+value "24"
 )
 ]
 )
@@ -728,7 +728,6 @@ stg "VerticalLayoutStrategy"
 f (Text
 uid 55,0
 va (VaSet
-font "courier,9,0"
 )
 xt "33000,17400,36400,18600"
 st "clock"
@@ -739,9 +738,9 @@ tm "CptPortNameMgr"
 dt (MLText
 uid 56,0
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
-xt "2000,11900,19000,12800"
+xt "2000,11900,15400,12900"
 st "clock      : IN     std_ulogic  ;"
 )
 thePort (LogicalPort
@@ -772,7 +771,6 @@ stg "RightVerticalLayoutStrategy"
 f (Text
 uid 60,0
 va (VaSet
-font "courier,9,0"
 )
 xt "39700,13400,47000,14600"
 st "lowpassOut"
@@ -784,9 +782,9 @@ tm "CptPortNameMgr"
 dt (MLText
 uid 61,0
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
-xt "2000,11000,30000,11900"
+xt "2000,11000,28000,12000"
 st "lowpassOut : OUT    unsigned (signalBitNb-1 DOWNTO 0) ;"
 )
 thePort (LogicalPort
@@ -819,7 +817,6 @@ stg "VerticalLayoutStrategy"
 f (Text
 uid 79,0
 va (VaSet
-font "courier,9,0"
 )
 xt "33000,19400,36300,20600"
 st "reset"
@@ -830,9 +827,9 @@ tm "CptPortNameMgr"
 dt (MLText
 uid 80,0
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
-xt "2000,12800,19000,13700"
+xt "2000,12800,15400,13800"
 st "reset      : IN     std_ulogic  ;"
 )
 thePort (LogicalPort
@@ -863,7 +860,6 @@ stg "VerticalLayoutStrategy"
 f (Text
 uid 86,0
 va (VaSet
-font "courier,9,0"
 )
 xt "33000,13400,38800,14600"
 st "lowpassIn"
@@ -874,9 +870,9 @@ tm "CptPortNameMgr"
 dt (MLText
 uid 87,0
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
-xt "2000,13700,29000,14600"
+xt "2000,13700,26500,14700"
 st "lowpassIn  : IN     unsigned (signalBitNb-1 DOWNTO 0)"
 )
 thePort (LogicalPort
@@ -909,20 +905,20 @@ stg "VerticalLayoutStrategy"
 first (Text
 uid 11,0
 va (VaSet
-font "courier,9,1"
+font "Verdana,9,1"
 )
-xt "32600,21800,41600,22700"
+xt "32600,21800,44100,23000"
 st "WaveformGenerator"
-blo "32600,22500"
+blo "32600,22800"
 )
 second (Text
 uid 12,0
 va (VaSet
-font "courier,9,1"
+font "Verdana,9,1"
 )
-xt "32600,22700,36100,23600"
+xt "32600,23000,37200,24200"
 st "lowpass"
-blo "32600,23400"
+blo "32600,24000"
 )
 )
 gi *68 (GenericInterface
@@ -933,13 +929,14 @@ uid 14,0
 text (MLText
 uid 15,0
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
-xt "32000,25600,45000,29200"
+xt "32000,25600,43200,29600"
 st "Generic Declarations
 
 signalBitNb positive 16  
-shiftBitNb  positive 12  "
+shiftBitNb  positive 12  
+"
 )
 header "Generic Declarations"
 showHdrWhenContentsEmpty 1
@@ -987,7 +984,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "36200,48000,50600,49000"
+xt "36200,48500,36200,48500"
 st "
 by %user on %dd %month %year
 "
@@ -1017,7 +1014,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "53200,44000,56800,45000"
+xt "53200,44500,53200,44500"
 st "
 Project:
 "
@@ -1047,7 +1044,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "36200,46000,52400,47000"
+xt "36200,46500,36200,46500"
 st "
 <enter diagram title here>
 "
@@ -1077,7 +1074,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "32200,46000,35800,47000"
+xt "32200,46500,32200,46500"
 st "
 Title:
 "
@@ -1107,7 +1104,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "53200,45200,66400,46200"
+xt "53200,45200,67300,46400"
 st "
 <enter comments here>
 "
@@ -1136,7 +1133,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "57200,44000,72800,45000"
+xt "57200,44500,57200,44500"
 st "
 <enter project name here>
 "
@@ -1165,7 +1162,7 @@ uid 38,0
 va (VaSet
 fg "32768,0,0"
 )
-xt "38000,44500,47000,45500"
+xt "37350,44400,47650,45600"
 st "
 <company name>
 "
@@ -1196,7 +1193,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "32200,47000,35200,48000"
+xt "32200,47500,32200,47500"
 st "
 Path:
 "
@@ -1226,7 +1223,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "32200,48000,35800,49000"
+xt "32200,48500,32200,48500"
 st "
 Edited:
 "
@@ -1256,7 +1253,7 @@ va (VaSet
 fg "0,0,32768"
 bg "0,0,32768"
 )
-xt "36200,47000,52400,48000"
+xt "36200,47500,36200,47500"
 st "
 %library/%unit/%view
 "
@@ -1300,9 +1297,9 @@ textVec [
 *81 (Text
 uid 49,0
 va (VaSet
-font "courier,8,1"
+font "Verdana,8,1"
 )
-xt "0,0,5400,1000"
+xt "0,0,6900,1000"
 st "Package List"
 blo "0,800"
 )
@@ -1310,7 +1307,7 @@ blo "0,800"
 uid 50,0
 va (VaSet
 )
-xt "0,1000,18600,4000"
+xt "0,1000,17500,4600"
 st "LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.numeric_std.all;"
@@ -1318,17 +1315,19 @@ tm "PackageList"
 )
 ]
 )
-windowSize "2,35,1387,985"
+windowSize "2,35,1389,985"
-viewArea "-1070,-1070,74579,51352"
+viewArea "-1100,-1100,74235,50510"
 cachedDiagramExtent "0,0,73000,49000"
 pageSetupInfo (PageSetupInfo
 ptrCmd ""
 toPrinter 1
 xMargin 49
 yMargin 49
+paperWidth 761
+paperHeight 1077
 windowsPaperWidth 761
 windowsPaperHeight 1077
-paperType "Letter (8.5\" x 11\")"
+paperType "A4"
 windowsPaperName "A4"
 exportedDirectories [
 "$HDS_PROJECT_DIR/HTMLExport"
@@ -1350,9 +1349,8 @@ xt "0,0,15000,5000"
 text (MLText
 va (VaSet
 fg "0,0,32768"
-font "courier,9,0"
 )
-xt "200,200,2200,1100"
+xt "200,200,3200,1400"
 st "
 Text
 "
@@ -1378,9 +1376,9 @@ autoResize 1
 text (MLText
 va (VaSet
 fg "0,0,32768"
-font "courier,8,0"
+font "Verdana,8,0"
 )
-xt "450,2150,1450,3050"
+xt "450,2150,1450,3150"
 st "
 Text
 "
@@ -1404,7 +1402,7 @@ title (TextAssociate
 ps "TopLeftStrategy"
 text (Text
 va (VaSet
-font "courier,9,1"
+font "Verdana,9,1"
 )
 xt "1000,1000,4400,2200"
 st "Panel0"
@@ -1433,7 +1431,7 @@ ps "CenterOffsetStrategy"
 stg "VerticalLayoutStrategy"
 first (Text
 va (VaSet
-font "courier,9,1"
+font "Verdana,9,1"
 )
 xt "22600,14800,27400,16000"
 st "<library>"
@@ -1441,7 +1439,7 @@ blo "22600,15800"
 )
 second (Text
 va (VaSet
-font "courier,9,1"
+font "Verdana,9,1"
 )
 xt "22600,16000,25900,17200"
 st "<cell>"
@@ -1454,7 +1452,7 @@ matrix (Matrix
 text (MLText
 va (VaSet
 isHidden 1
-font "courier,8,0"
+font "Verdana,8,0"
 )
 xt "0,12000,0,12000"
 )
@@ -1482,7 +1480,7 @@ ps "CptPortTextPlaceStrategy"
 stg "VerticalLayoutStrategy"
 f (Text
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
 xt "0,750,1500,1650"
 st "In0"
@@ -1492,7 +1490,7 @@ tm "CptPortNameMgr"
 )
 dt (MLText
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
 )
 thePort (LogicalPort
@@ -1520,7 +1518,7 @@ ps "CptPortTextPlaceStrategy"
 stg "VerticalLayoutStrategy"
 f (Text
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
 xt "0,750,3500,1650"
 st "Buffer0"
@@ -1530,7 +1528,7 @@ tm "CptPortNameMgr"
 )
 dt (MLText
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
 )
 thePort (LogicalPort
@@ -1550,44 +1548,44 @@ stg "SymDeclLayoutStrategy"
 declLabel (Text
 uid 2,0
 va (VaSet
-font "courier,8,1"
+font "Verdana,8,1"
 )
-xt "0,9000,5400,10000"
+xt "0,9000,7000,10000"
 st "Declarations"
 blo "0,9800"
 )
 portLabel (Text
 uid 3,0
 va (VaSet
-font "courier,8,1"
+font "Verdana,8,1"
 )
-xt "0,10000,2700,11000"
+xt "0,10000,3400,11000"
 st "Ports:"
 blo "0,10800"
 )
 externalLabel (Text
 uid 4,0
 va (VaSet
-font "courier,8,1"
+font "Verdana,8,1"
 )
-xt "0,14600,2500,15500"
+xt "0,14600,3000,15600"
 st "User:"
-blo "0,15300"
+blo "0,15400"
 )
 internalLabel (Text
 uid 6,0
 va (VaSet
 isHidden 1
-font "courier,8,1"
+font "Verdana,8,1"
 )
-xt "0,9000,5800,10000"
+xt "0,9000,7600,10000"
 st "Internal User:"
 blo "0,9800"
 )
 externalText (MLText
 uid 5,0
 va (VaSet
-font "courier,8,0"
+font "Verdana,8,0"
 )
 xt "2000,15500,2000,15500"
 tm "SyDeclarativeTextMgr"
@@ -1596,12 +1594,12 @@ internalText (MLText
 uid 7,0
 va (VaSet
 isHidden 1
-font "courier,8,0"
+font "Verdana,8,0"
 )
 xt "0,9000,0,9000"
 tm "SyDeclarativeTextMgr"
 )
 )
-lastUid 181,0
+lastUid 227,0
-activeModelName "Symbol"
+activeModelName "Symbol:GEN"
 )

01-WaveformGenerator/WaveformGenerator/hds/waveform@gen/struct.bd

@@ -68,7 +68,7 @@ value "signalBitNb"
 (GiElement
 name "shiftBitNb"
 type "positive"
-value "10"
+value "5"
 )
 ]
 mwi 0
@@ -105,23 +105,23 @@ value " "
 )
 (vvPair
 variable "HDLDir"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hdl"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd.info"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd.user"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds"
 )
 (vvPair
 variable "appl"
@@ -145,15 +145,15 @@ value "%(unit)_%(view)_config"
 )
 (vvPair
 variable "d"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen"
 )
 (vvPair
 variable "d_logical"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveformGen"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveformGen"
 )
 (vvPair
 variable "date"
-value "28.04.2023"
+value "01.03.2024"
 )
 (vvPair
 variable "day"
@@ -165,7 +165,7 @@ value "vendredi"
 )
 (vvPair
 variable "dd"
-value "28"
+value "01"
 )
 (vvPair
 variable "designName"
@@ -193,11 +193,11 @@ value "struct"
 )
 (vvPair
 variable "graphical_source_author"
-value "axel.amand"
+value "remi.heredero"
 )
 (vvPair
 variable "graphical_source_date"
-value "28.04.2023"
+value "01.03.2024"
 )
 (vvPair
 variable "graphical_source_group"
@@ -205,11 +205,11 @@ value "UNKNOWN"
 )
 (vvPair
 variable "graphical_source_host"
-value "WE7860"
+value "WE2330808"
 )
 (vvPair
 variable "graphical_source_time"
-value "14:40:08"
+value "15:15:34"
 )
 (vvPair
 variable "group"
@@ -217,7 +217,7 @@ value "UNKNOWN"
 )
 (vvPair
 variable "host"
-value "WE7860"
+value "WE2330808"
 )
 (vvPair
 variable "language"
@@ -245,7 +245,7 @@ value "U:\\SEm_curves\\Synthesis"
 )
 (vvPair
 variable "mm"
-value "04"
+value "03"
 )
 (vvPair
 variable "module_name"
@@ -253,19 +253,19 @@ value "waveformGen"
 )
 (vvPair
 variable "month"
-value "avr."
+value "mars"
 )
 (vvPair
 variable "month_long"
-value "avril"
+value "mars"
 )
 (vvPair
 variable "p"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveform@gen\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveformGen\\struct.bd"
+value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator\\hds\\waveformGen\\struct.bd"
 )
 (vvPair
 variable "package_name"
@@ -341,7 +341,7 @@ value "struct"
 )
 (vvPair
 variable "time"
-value "14:40:08"
+value "15:15:34"
 )
 (vvPair
 variable "unit"
@@ -349,7 +349,7 @@ value "waveformGen"
 )
 (vvPair
 variable "user"
-value "axel.amand"
+value "remi.heredero"
 )
 (vvPair
 variable "version"
@@ -361,11 +361,11 @@ value "struct"
 )
 (vvPair
 variable "year"
-value "2023"
+value "2024"
 )
 (vvPair
 variable "yy"
-value "23"
+value "24"
 )
 ]
 )
@@ -1726,9 +1726,9 @@ uid 1023,0
 va (VaSet
 font "Arial,9,0"
 )
-xt "81000,46400,83500,47300"
+xt "81000,46400,83700,47600"
 st "clock"
-blo "81000,47100"
+blo "81000,47300"
 )
 )
 thePort (LogicalPort
@@ -1761,10 +1761,10 @@ uid 1027,0
 va (VaSet
 font "Arial,9,0"
 )
-xt "89500,42400,95000,43300"
+xt "89200,42400,95000,43600"
 st "lowpassOut"
 ju 2
-blo "95000,43100"
+blo "95000,43300"
 )
 )
 thePort (LogicalPort
@@ -1799,9 +1799,9 @@ uid 1031,0
 va (VaSet
 font "Arial,9,0"
 )
-xt "81000,48400,83500,49300"
+xt "81000,48400,83600,49600"
 st "reset"
-blo "81000,49100"
+blo "81000,49300"
 )
 )
 thePort (LogicalPort
@@ -1834,9 +1834,9 @@ uid 1035,0
 va (VaSet
 font "Arial,9,0"
 )
-xt "81000,42400,85500,43300"
+xt "81000,42400,85600,43600"
 st "lowpassIn"
-blo "81000,43100"
+blo "81000,43300"
 )
 )
 thePort (LogicalPort
@@ -1910,7 +1910,8 @@ va (VaSet
 )
 xt "80000,54600,102900,57000"
 st "signalBitNb = signalBitNb    ( positive )  
-shiftBitNb  = 10             ( positive )  "
+shiftBitNb  = 5              ( positive )  
+"
 )
 header ""
 )
@@ -1923,7 +1924,7 @@ value "signalBitNb"
 (GiElement
 name "shiftBitNb"
 type "positive"
-value "10"
+value "5"
 )
 ]
 )
@@ -2954,8 +2955,8 @@ tm "BdCompilerDirectivesTextMgr"
 ]
 associable 1
 )
-windowSize "-8,-8,1928,1048"
+windowSize "0,0,1921,1056"
-viewArea "-4571,-1604,138105,75916"
+viewArea "-4600,-1600,137612,74000"
 cachedDiagramExtent "-24700,0,129400,74000"
 pageSetupInfo (PageSetupInfo
 ptrCmd ""
@@ -2979,7 +2980,7 @@ boundaryWidth 0
 )
 hasePageBreakOrigin 1
 pageBreakOrigin "-3000,0"
-lastUid 1289,0
+lastUid 1316,0
 defaultCommentText (CommentText
 shape (Rectangle
 layer 0

01-WaveformGenerator/WaveformGenerator/hds/waveform@gen/struct.bd.lck

@@ -1,6 +0,0 @@
-EDIT_LOCK
-remi.heredero
-UNKNOWN
-WE2330808
-15212
-01.03.2024-14:26:40.915000

01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg

@@ -3,7 +3,7 @@
 --
 -- Created:
 --          by - remi.heredero.UNKNOWN (WE2330808)
---          at - 14:26:40 01.03.2024
+--          at - 15:12:57 01.03.2024
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
 --
@@ -20,8 +20,8 @@ ARCHITECTURE struct OF waveformGen_tb IS
     constant bitNb: positive := 16;
     constant signalBitNb: positive := 16;
     constant phaseBitNb: positive := 16;
-    constant clockFrequency: real := 60.0E6;
+    --constant clockFrequency: real := 60.0E6;
-    --constant clockFrequency: real := 66.0E6;
+    constant clockFrequency: real := 66.0E6;
 
     -- Internal signal declarations
     SIGNAL clock    : std_ulogic;

01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd

@@ -173,7 +173,7 @@ value "WE2330808"
 )
 (vvPair
 variable "graphical_source_time"
-value "14:26:40"
+value "15:12:57"
 )
 (vvPair
 variable "group"
@@ -301,7 +301,7 @@ value "struct"
 )
 (vvPair
 variable "time"
-value "14:26:40"
+value "15:12:57"
 )
 (vvPair
 variable "unit"
@@ -2743,8 +2743,9 @@ xt "2000,7700,26900,13700"
 st "constant bitNb: positive := 16;
 constant signalBitNb: positive := 16;
 constant phaseBitNb: positive := 16;
-constant clockFrequency: real := 60.0E6;
+--constant clockFrequency: real := 60.0E6;
---constant clockFrequency: real := 66.0E6;"
+constant clockFrequency: real := 66.0E6;
+"
 tm "BdDeclarativeTextMgr"
 )
 diagSignalLabel (Text

01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.bak

@@ -173,7 +173,7 @@ value "WE2330808"
 )
 (vvPair
 variable "graphical_source_time"
-value "13:13:41"
+value "14:26:40"
 )
 (vvPair
 variable "group"
@@ -301,7 +301,7 @@ value "struct"
 )
 (vvPair
 variable "time"
-value "13:13:41"
+value "14:26:40"
 )
 (vvPair
 variable "unit"
@@ -771,7 +771,7 @@ declText (MLText
 uid 595,0
 va (VaSet
 )
-xt "2000,21800,29200,23000"
+xt "2000,23000,29200,24200"
 st "SIGNAL step     : unsigned(bitNb-1 DOWNTO 0)
 "
 )
@@ -1241,7 +1241,7 @@ declText (MLText
 uid 1264,0
 va (VaSet
 )
-xt "2000,20600,32900,21800"
+xt "2000,21800,32900,23000"
 st "SIGNAL square   : unsigned(signalBitNb-1 DOWNTO 0)
 "
 )
@@ -1259,7 +1259,7 @@ declText (MLText
 uid 1309,0
 va (VaSet
 )
-xt "2000,23000,32700,24200"
+xt "2000,24200,32700,25400"
 st "SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0)
 "
 )
@@ -1282,7 +1282,25 @@ st "SIGNAL polygon  : unsigned(signalBitNb-1 DOWNTO 0)
 "
 )
 )
-*37 (Wire
+*37 (Net
+uid 1404,0
+decl (Decl
+n "sine"
+t "unsigned"
+b "(signalBitNb-1 DOWNTO 0)"
+o 9
+suid 13,0
+)
+declText (MLText
+uid 1405,0
+va (VaSet
+)
+xt "2000,20600,32200,21800"
+st "SIGNAL sine     : unsigned(signalBitNb-1 DOWNTO 0)
+"
+)
+)
+*38 (Wire
 uid 47,0
 shape (OrthoPolyLine
 uid 48,0
@@ -1321,7 +1339,7 @@ tm "WireNameMgr"
 )
 on &1
 )
-*38 (Wire
+*39 (Wire
 uid 55,0
 shape (OrthoPolyLine
 uid 56,0
@@ -1360,7 +1378,7 @@ tm "WireNameMgr"
 )
 on &2
 )
-*39 (Wire
+*40 (Wire
 uid 596,0
 shape (OrthoPolyLine
 uid 597,0
@@ -1401,7 +1419,7 @@ tm "WireNameMgr"
 )
 on &18
 )
-*40 (Wire
+*41 (Wire
 uid 702,0
 shape (OrthoPolyLine
 uid 703,0
@@ -1440,7 +1458,7 @@ tm "WireNameMgr"
 )
 on &19
 )
-*41 (Wire
+*42 (Wire
 uid 1182,0
 shape (OrthoPolyLine
 uid 1183,0
@@ -1481,7 +1499,7 @@ tm "WireNameMgr"
 )
 on &33
 )
-*42 (Wire
+*43 (Wire
 uid 1265,0
 shape (OrthoPolyLine
 uid 1266,0
@@ -1522,7 +1540,7 @@ tm "WireNameMgr"
 )
 on &34
 )
-*43 (Wire
+*44 (Wire
 uid 1310,0
 shape (OrthoPolyLine
 uid 1311,0
@@ -1563,7 +1581,7 @@ tm "WireNameMgr"
 )
 on &35
 )
-*44 (Wire
+*45 (Wire
 uid 1357,0
 shape (OrthoPolyLine
 uid 1358,0
@@ -1604,6 +1622,47 @@ tm "WireNameMgr"
 )
 on &36
 )
+*46 (Wire
+uid 1406,0
+shape (OrthoPolyLine
+uid 1407,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55750,26000,58000,38000"
+pts [
+"55750,26000"
+"58000,26000"
+"58000,38000"
+]
+)
+start &25
+end &14
+sat 32
+eat 1
+sty 1
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 1410,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1411,0
+va (VaSet
+font "Arial,12,0"
+)
+xt "57750,24500,60850,26000"
+st "sine"
+blo "57750,25700"
+tm "WireNameMgr"
+)
+)
+on &37
+)
 ]
 bg "65535,65535,65535"
 grid (Grid
@@ -1616,11 +1675,11 @@ xShown 1
 yShown 1
 color "26368,26368,26368"
 )
-packageList *45 (PackageList
+packageList *47 (PackageList
 uid 142,0
 stg "VerticalLayoutStrategy"
 textVec [
-*46 (Text
+*48 (Text
 uid 143,0
 va (VaSet
 font "Arial,8,1"
@@ -1629,7 +1688,7 @@ xt "0,0,6500,900"
 st "Package List"
 blo "0,700"
 )
-*47 (MLText
+*49 (MLText
 uid 144,0
 va (VaSet
 )
@@ -1645,7 +1704,7 @@ compDirBlock (MlTextGroup
 uid 145,0
 stg "VerticalLayoutStrategy"
 textVec [
-*48 (Text
+*50 (Text
 uid 146,0
 va (VaSet
 isHidden 1
@@ -1655,7 +1714,7 @@ xt "20000,0,30000,900"
 st "Compiler Directives"
 blo "20000,700"
 )
-*49 (Text
+*51 (Text
 uid 147,0
 va (VaSet
 isHidden 1
@@ -1665,7 +1724,7 @@ xt "20000,1000,31500,1900"
 st "Pre-module directives:"
 blo "20000,1700"
 )
-*50 (MLText
+*52 (MLText
 uid 148,0
 va (VaSet
 isHidden 1
@@ -1675,7 +1734,7 @@ st "`resetall
 `timescale 1ns/10ps"
 tm "BdCompilerDirectivesTextMgr"
 )
-*51 (Text
+*53 (Text
 uid 149,0
 va (VaSet
 isHidden 1
@@ -1685,7 +1744,7 @@ xt "20000,4000,32000,4900"
 st "Post-module directives:"
 blo "20000,4700"
 )
-*52 (MLText
+*54 (MLText
 uid 150,0
 va (VaSet
 isHidden 1
@@ -1693,7 +1752,7 @@ isHidden 1
 xt "20000,0,20000,0"
 tm "BdCompilerDirectivesTextMgr"
 )
-*53 (Text
+*55 (Text
 uid 151,0
 va (VaSet
 isHidden 1
@@ -1703,7 +1762,7 @@ xt "20000,5000,31500,5900"
 st "End-module directives:"
 blo "20000,5700"
 )
-*54 (MLText
+*56 (MLText
 uid 152,0
 va (VaSet
 isHidden 1
@@ -1714,7 +1773,7 @@ tm "BdCompilerDirectivesTextMgr"
 ]
 associable 1
 )
-windowSize "0,0,1921,1056"
+windowSize "0,24,1921,1080"
 viewArea "-1200,4500,107152,62100"
 cachedDiagramExtent "0,0,81000,55000"
 pageSetupInfo (PageSetupInfo
@@ -1740,7 +1799,7 @@ boundaryWidth 0
 )
 hasePageBreakOrigin 1
 pageBreakOrigin "0,0"
-lastUid 1364,0
+lastUid 1413,0
 defaultCommentText (CommentText
 shape (Rectangle
 layer 0
@@ -1827,7 +1886,7 @@ ttg (MlTextGroup
 ps "CenterOffsetStrategy"
 stg "VerticalLayoutStrategy"
 textVec [
-*55 (Text
+*57 (Text
 va (VaSet
 font "Arial,9,0"
 )
@@ -1836,7 +1895,7 @@ st "<library>"
 blo "1700,4200"
 tm "BdLibraryNameMgr"
 )
-*56 (Text
+*58 (Text
 va (VaSet
 font "Arial,9,0"
 )
@@ -1845,7 +1904,7 @@ st "<block>"
 blo "1700,5400"
 tm "BlkNameMgr"
 )
-*57 (Text
+*59 (Text
 va (VaSet
 font "Arial,9,0"
 )
@@ -1883,21 +1942,21 @@ ttg (MlTextGroup
 ps "CenterOffsetStrategy"
 stg "VerticalLayoutStrategy"
 textVec [
-*58 (Text
+*60 (Text
 va (VaSet
 )
 xt "1000,3500,3300,4500"
 st "Library"
 blo "1000,4300"
 )
-*59 (Text
+*61 (Text
 va (VaSet
 )
 xt "1000,4500,7000,5500"
 st "MWComponent"
 blo "1000,5300"
 )
-*60 (Text
+*62 (Text
 va (VaSet
 )
 xt "1000,5500,1600,6500"
@@ -1941,7 +2000,7 @@ ttg (MlTextGroup
 ps "CenterOffsetStrategy"
 stg "VerticalLayoutStrategy"
 textVec [
-*61 (Text
+*63 (Text
 va (VaSet
 )
 xt "1250,3500,3550,4500"
@@ -1949,7 +2008,7 @@ st "Library"
 blo "1250,4300"
 tm "BdLibraryNameMgr"
 )
-*62 (Text
+*64 (Text
 va (VaSet
 )
 xt "1250,4500,6750,5500"
@@ -1957,7 +2016,7 @@ st "SaComponent"
 blo "1250,5300"
 tm "CptNameMgr"
 )
-*63 (Text
+*65 (Text
 va (VaSet
 )
 xt "1250,5500,1850,6500"
@@ -1995,21 +2054,21 @@ ttg (MlTextGroup
 ps "CenterOffsetStrategy"
 stg "VerticalLayoutStrategy"
 textVec [
-*64 (Text
+*66 (Text
 va (VaSet
 )
 xt "950,3500,3250,4500"
 st "Library"
 blo "950,4300"
 )
-*65 (Text
+*67 (Text
 va (VaSet
 )
 xt "950,4500,7050,5500"
 st "VhdlComponent"
 blo "950,5300"
 )
-*66 (Text
+*68 (Text
 va (VaSet
 )
 xt "950,5500,1550,6500"
@@ -2049,21 +2108,21 @@ ttg (MlTextGroup
 ps "CenterOffsetStrategy"
 stg "VerticalLayoutStrategy"
 textVec [
-*67 (Text
+*69 (Text
 va (VaSet
 )
 xt "450,3500,2750,4500"
 st "Library"
 blo "450,4300"
 )
-*68 (Text
+*70 (Text
 va (VaSet
 )
 xt "450,4500,7550,5500"
 st "VerilogComponent"
 blo "450,5300"
 )
-*69 (Text
+*71 (Text
 va (VaSet
 )
 xt "450,5500,1050,6500"
@@ -2101,7 +2160,7 @@ ttg (MlTextGroup
 ps "CenterOffsetStrategy"
 stg "VerticalLayoutStrategy"
 textVec [
-*70 (Text
+*72 (Text
 va (VaSet
 )
 xt "3400,4000,4600,5000"
@@ -2109,7 +2168,7 @@ st "eb1"
 blo "3400,4800"
 tm "HdlTextNameMgr"
 )
-*71 (Text
+*73 (Text
 va (VaSet
 )
 xt "3400,5000,3800,6000"
@@ -2506,7 +2565,7 @@ decls (MlTextGroup
 ps "BottomRightOffsetStrategy"
 stg "VerticalLayoutStrategy"
 textVec [
-*72 (Text
+*74 (Text
 va (VaSet
 font "Arial,8,1"
 )
@@ -2514,7 +2573,7 @@ xt "14100,20000,22000,21000"
 st "Frame Declarations"
 blo "14100,20800"
 )
-*73 (MLText
+*75 (MLText
 va (VaSet
 )
 xt "14100,21000,14100,21000"
@@ -2566,7 +2625,7 @@ decls (MlTextGroup
 ps "BottomRightOffsetStrategy"
 stg "VerticalLayoutStrategy"
 textVec [
-*74 (Text
+*76 (Text
 va (VaSet
 font "Arial,8,1"
 )
@@ -2574,7 +2633,7 @@ xt "14100,20000,22000,21000"
 st "Frame Declarations"
 blo "14100,20800"
 )
-*75 (MLText
+*77 (MLText
 va (VaSet
 )
 xt "14100,21000,14100,21000"
@@ -2685,8 +2744,7 @@ st "constant bitNb: positive := 16;
 constant signalBitNb: positive := 16;
 constant phaseBitNb: positive := 16;
 constant clockFrequency: real := 60.0E6;
---constant clockFrequency: real := 66.0E6;
+--constant clockFrequency: real := 66.0E6;"
-"
 tm "BdDeclarativeTextMgr"
 )
 diagSignalLabel (Text
@@ -2719,46 +2777,46 @@ tm "BdDeclarativeTextMgr"
 )
 commonDM (CommonDM
 ldm (LogicalDM
-suid 12,0
+suid 13,0
 usingSuid 1
-emptyRow *76 (LEmptyRow
+emptyRow *78 (LEmptyRow
 )
 uid 717,0
 optionalChildren [
-*77 (RefLabelRowHdr
+*79 (RefLabelRowHdr
 )
-*78 (TitleRowHdr
+*80 (TitleRowHdr
 )
-*79 (FilterRowHdr
+*81 (FilterRowHdr
 )
-*80 (RefLabelColHdr
+*82 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*81 (RowExpandColHdr
+*83 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*82 (GroupColHdr
+*84 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*83 (NameColHdr
+*85 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*84 (ModeColHdr
+*86 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*85 (TypeColHdr
+*87 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*86 (BoundsColHdr
+*88 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*87 (InitColHdr
+*89 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*88 (EolColHdr
+*90 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*89 (LeafLogPort
+*91 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
@@ -2770,7 +2828,7 @@ suid 1,0
 )
 uid 708,0
 )
-*90 (LeafLogPort
+*92 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
@@ -2782,7 +2840,7 @@ suid 2,0
 )
 uid 710,0
 )
-*91 (LeafLogPort
+*93 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
@@ -2795,7 +2853,7 @@ suid 3,0
 )
 uid 712,0
 )
-*92 (LeafLogPort
+*94 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
@@ -2807,7 +2865,7 @@ suid 4,0
 )
 uid 714,0
 )
-*93 (LeafLogPort
+*95 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
@@ -2820,7 +2878,7 @@ suid 5,0
 )
 uid 1188,0
 )
-*94 (LeafLogPort
+*96 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
@@ -2833,7 +2891,7 @@ suid 10,0
 )
 uid 1271,0
 )
-*95 (LeafLogPort
+*97 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
@@ -2846,7 +2904,7 @@ suid 11,0
 )
 uid 1316,0
 )
-*96 (LeafLogPort
+*98 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
@@ -2859,6 +2917,19 @@ suid 12,0
 )
 uid 1363,0
 )
+*99 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "sine"
+t "unsigned"
+b "(signalBitNb-1 DOWNTO 0)"
+o 9
+suid 13,0
+)
+)
+uid 1412,0
+)
 ]
 )
 pdm (PhysicalDM
@@ -2866,7 +2937,7 @@ displayShortBounds 1
 editShortBounds 1
 uid 730,0
 optionalChildren [
-*97 (Sheet
+*100 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
 cellColor "49152,49152,49152"
@@ -2883,80 +2954,86 @@ cellColor "39936,56832,65280"
 fontColor "0,0,0"
 font "Tahoma,10,0"
 )
-emptyMRCItem *98 (MRCItem
+emptyMRCItem *101 (MRCItem
-litem &76
+litem &78
-pos 8
+pos 9
 dimension 20
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02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs

@@ -1280,6 +1280,7 @@ projectPaths [
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02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcalculatepolynom_entity.vhg

@@ -0,0 +1,34 @@
+-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:14 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY interpolatorCalculatePolynom IS
+    GENERIC( 
+        signalBitNb       : positive := 16;
+        coeffBitNb        : positive := 16;
+        oversamplingBitNb : positive := 8
+    );
+    PORT( 
+        clock          : IN     std_ulogic;
+        reset          : IN     std_ulogic;
+        restartPolynom : IN     std_ulogic;
+        d              : IN     signed (coeffBitNb-1 DOWNTO 0);
+        sampleOut      : OUT    signed (signalBitNb-1 DOWNTO 0);
+        c              : IN     signed (coeffBitNb-1 DOWNTO 0);
+        b              : IN     signed (coeffBitNb-1 DOWNTO 0);
+        a              : IN     signed (coeffBitNb-1 DOWNTO 0);
+        en             : IN     std_ulogic
+    );
+
+-- Declarations
+
+END interpolatorCalculatePolynom ;
+

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcoefficients_entity.vhg

@@ -0,0 +1,33 @@
+-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:20 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY interpolatorCoefficients IS
+    GENERIC( 
+        bitNb      : positive := 16;
+        coeffBitNb : positive := 16
+    );
+    PORT( 
+        sample1           : IN     signed (bitNb-1 DOWNTO 0);
+        sample2           : IN     signed (bitNb-1 DOWNTO 0);
+        sample3           : IN     signed (bitNb-1 DOWNTO 0);
+        sample4           : IN     signed (bitNb-1 DOWNTO 0);
+        a                 : OUT    signed (coeffBitNb-1 DOWNTO 0);
+        b                 : OUT    signed (coeffBitNb-1 DOWNTO 0);
+        c                 : OUT    signed (coeffBitNb-1 DOWNTO 0);
+        d                 : OUT    signed (coeffBitNb-1 DOWNTO 0);
+        interpolateLinear : IN     std_ulogic
+    );
+
+-- Declarations
+
+END interpolatorCoefficients ;
+

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorshiftregister_entity.vhg

@@ -0,0 +1,31 @@
+-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:24 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY interpolatorShiftRegister IS
+    GENERIC( 
+        signalBitNb : positive := 16
+    );
+    PORT( 
+        clock        : IN     std_ulogic;
+        reset        : IN     std_ulogic;
+        shiftSamples : IN     std_ulogic;
+        sampleIn     : IN     signed (signalBitNb-1 DOWNTO 0);
+        sample1      : OUT    signed (signalBitNb-1 DOWNTO 0);
+        sample2      : OUT    signed (signalBitNb-1 DOWNTO 0);
+        sample3      : OUT    signed (signalBitNb-1 DOWNTO 0);
+        sample4      : OUT    signed (signalBitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END interpolatorShiftRegister ;
+

02-SplineInterpolator/SplineInterpolator/hdl/interpolatortrigger_entity.vhg

@@ -0,0 +1,27 @@
+-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:28 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY interpolatorTrigger IS
+    GENERIC( 
+        counterBitNb : positive := 4
+    );
+    PORT( 
+        triggerOut : OUT    std_ulogic;
+        clock      : IN     std_ulogic;
+        reset      : IN     std_ulogic;
+        en         : IN     std_ulogic
+    );
+
+-- Declarations
+
+END interpolatorTrigger ;
+

02-SplineInterpolator/SplineInterpolator/hdl/offsettounsigned_entity.vhg

@@ -0,0 +1,25 @@
+-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:32 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY offsetToUnsigned IS
+    GENERIC( 
+        bitNb : positive := 16
+    );
+    PORT( 
+        unsignedOut : OUT    unsigned (bitNb-1 DOWNTO 0);
+        signedIn    : IN     signed (bitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END offsetToUnsigned ;
+

02-SplineInterpolator/SplineInterpolator/hdl/resizer_entity.vhg

@@ -0,0 +1,26 @@
+-- VHDL Entity SplineInterpolator.resizer.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:36 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY resizer IS
+    GENERIC( 
+        inputBitNb  : positive := 16;
+        outputBitNb : positive := 16
+    );
+    PORT( 
+        resizeOut : OUT    unsigned (outputBitNb-1 DOWNTO 0);
+        resizeIn  : IN     unsigned (inputBitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END resizer ;
+

02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd

@@ -1,4 +1,24 @@
 ARCHITECTURE studentVersion OF resizer IS
+
+	signal mySignal : unsigned(outputBitNb-1 downto 0);
+	
+--------------------------------------------------------------------------------
 BEGIN
-  resizeOut <= (others => '0');
+
+INPUT_BIGGER: if inputBitNb >= outputBitNb generate
+	process(resizeIn)
+	begin
+		mySignal <= resize(shift_right(resizeIn, inputBitNb - outputBitNb), outputBitNb);
+	end process;
+end generate INPUT_BIGGER;
+
+OUTPUT_BIGGER: if inputBitNb <= outputBitNb generate
+	process(resizeIn)
+	begin
+		mySignal <= shift_left(resize(resizeIn, outputBitNb), outputBitNb - inputBitNb);
+	end process;
+end generate OUTPUT_BIGGER;
+
+	resizeOut <= mySignal;
+
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd

@@ -1,15 +1,25 @@
 ARCHITECTURE studentVersion OF sineTable IS
 
   signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
+  signal phaseTableAddress2 : unsigned(tableAddressBitNb-1 downto 0);
   signal quarterSine : signed(sine'range);
 
 BEGIN
 
   phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
 
-  quarterTable: process(phaseTableAddress)
+  sequenceTable: process(phase)
   begin
-    case to_integer(phaseTableAddress) is
+    if phase(phase'high-1) = '1' then
+      phaseTableAddress2 <= 8 - phaseTableAddress;
+    else
+      phaseTableAddress2 <= phaseTableAddress;
+    end if;
+  end process sequenceTable;
+
+  quarterTable: process(phaseTableAddress2)
+  begin
+    case to_integer(phaseTableAddress2) is
       when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
       when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
       when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
@@ -22,6 +32,15 @@ BEGIN
     end case;
   end process quarterTable;
 
-  sine <= (others => '0');
+  invert: process(quarterSine)
+  begin
+    if phase(phase'high) = '1' then
+      sine <= NOT quarterSine;
+    else
+      sine <= quarterSine;
+    end if;
+  end process invert;
+  
+  --sine <= quarterSine;
 
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/sinegen_entity.vhg

@@ -0,0 +1,31 @@
+-- VHDL Entity SplineInterpolator.sineGen.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:40 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY sineGen IS
+    GENERIC( 
+        signalBitNb : positive := 16;
+        phaseBitNb  : positive := 10
+    );
+    PORT( 
+        clock    : IN     std_ulogic;
+        reset    : IN     std_ulogic;
+        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
+        sawtooth : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END sineGen ;
+

02-SplineInterpolator/SplineInterpolator/hdl/sinegen_struct.vhg

@@ -0,0 +1,307 @@
+--
+-- VHDL Architecture SplineInterpolator.sineGen.struct
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:42:04 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+LIBRARY SplineInterpolator;
+LIBRARY WaveformGenerator;
+
+ARCHITECTURE struct OF sineGen IS
+
+    -- Architecture declarations
+    constant tableAddressBitNb : positive := 3;
+    constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb;
+    constant coeffBitNb : positive := signalBitNb+4;
+
+    -- Internal signal declarations
+    SIGNAL a           : signed(coeffBitNb-1 DOWNTO 0);
+    SIGNAL b           : signed(coeffBitNb-1 DOWNTO 0);
+    SIGNAL c           : signed(coeffBitNb-1 DOWNTO 0);
+    SIGNAL d           : signed(coeffBitNb-1 DOWNTO 0);
+    SIGNAL logic0      : std_ulogic;
+    SIGNAL logic1      : std_ulogic;
+    SIGNAL newPolynom  : std_ulogic;
+    SIGNAL phase       : unsigned(phaseBitNb-1 DOWNTO 0);
+    SIGNAL sample1     : signed(signalBitNb-1 DOWNTO 0);
+    SIGNAL sample2     : signed(signalBitNb-1 DOWNTO 0);
+    SIGNAL sample3     : signed(signalBitNb-1 DOWNTO 0);
+    SIGNAL sample4     : signed(signalBitNb-1 DOWNTO 0);
+    SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0);
+    SIGNAL sineSigned  : signed(signalBitNb-1 DOWNTO 0);
+
+    -- Implicit buffer signal declarations
+    SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0);
+
+
+    -- Component Declarations
+    COMPONENT interpolatorCalculatePolynom
+    GENERIC (
+        signalBitNb       : positive := 16;
+        coeffBitNb        : positive := 16;
+        oversamplingBitNb : positive := 8
+    );
+    PORT (
+        clock          : IN     std_ulogic ;
+        reset          : IN     std_ulogic ;
+        restartPolynom : IN     std_ulogic ;
+        d              : IN     signed (coeffBitNb-1 DOWNTO 0);
+        sampleOut      : OUT    signed (signalBitNb-1 DOWNTO 0);
+        c              : IN     signed (coeffBitNb-1 DOWNTO 0);
+        b              : IN     signed (coeffBitNb-1 DOWNTO 0);
+        a              : IN     signed (coeffBitNb-1 DOWNTO 0);
+        en             : IN     std_ulogic 
+    );
+    END COMPONENT;
+    COMPONENT interpolatorCoefficients
+    GENERIC (
+        bitNb      : positive := 16;
+        coeffBitNb : positive := 16
+    );
+    PORT (
+        sample1           : IN     signed (bitNb-1 DOWNTO 0);
+        sample2           : IN     signed (bitNb-1 DOWNTO 0);
+        sample3           : IN     signed (bitNb-1 DOWNTO 0);
+        sample4           : IN     signed (bitNb-1 DOWNTO 0);
+        a                 : OUT    signed (coeffBitNb-1 DOWNTO 0);
+        b                 : OUT    signed (coeffBitNb-1 DOWNTO 0);
+        c                 : OUT    signed (coeffBitNb-1 DOWNTO 0);
+        d                 : OUT    signed (coeffBitNb-1 DOWNTO 0);
+        interpolateLinear : IN     std_ulogic 
+    );
+    END COMPONENT;
+    COMPONENT interpolatorShiftRegister
+    GENERIC (
+        signalBitNb : positive := 16
+    );
+    PORT (
+        clock        : IN     std_ulogic ;
+        reset        : IN     std_ulogic ;
+        shiftSamples : IN     std_ulogic ;
+        sampleIn     : IN     signed (signalBitNb-1 DOWNTO 0);
+        sample1      : OUT    signed (signalBitNb-1 DOWNTO 0);
+        sample2      : OUT    signed (signalBitNb-1 DOWNTO 0);
+        sample3      : OUT    signed (signalBitNb-1 DOWNTO 0);
+        sample4      : OUT    signed (signalBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT interpolatorTrigger
+    GENERIC (
+        counterBitNb : positive := 4
+    );
+    PORT (
+        triggerOut : OUT    std_ulogic ;
+        clock      : IN     std_ulogic ;
+        reset      : IN     std_ulogic ;
+        en         : IN     std_ulogic 
+    );
+    END COMPONENT;
+    COMPONENT offsetToUnsigned
+    GENERIC (
+        bitNb : positive := 16
+    );
+    PORT (
+        unsignedOut : OUT    unsigned (bitNb-1 DOWNTO 0);
+        signedIn    : IN     signed (bitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT resizer
+    GENERIC (
+        inputBitNb  : positive := 16;
+        outputBitNb : positive := 16
+    );
+    PORT (
+        resizeOut : OUT    unsigned (outputBitNb-1 DOWNTO 0);
+        resizeIn  : IN     unsigned (inputBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT sineTable
+    GENERIC (
+        inputBitNb        : positive := 16;
+        outputBitNb       : positive := 16;
+        tableAddressBitNb : positive := 3
+    );
+    PORT (
+        sine  : OUT    signed (outputBitNb-1 DOWNTO 0);
+        phase : IN     unsigned (inputBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT sawtoothGen
+    GENERIC (
+        bitNb : positive := 16
+    );
+    PORT (
+        sawtooth : OUT    unsigned (bitNb-1 DOWNTO 0);
+        clock    : IN     std_ulogic ;
+        reset    : IN     std_ulogic ;
+        step     : IN     unsigned (bitNb-1 DOWNTO 0);
+        en       : IN     std_ulogic 
+    );
+    END COMPONENT;
+    COMPONENT sawtoothToSquare
+    GENERIC (
+        bitNb : positive := 16
+    );
+    PORT (
+        square   : OUT    unsigned (bitNb-1 DOWNTO 0);
+        sawtooth : IN     unsigned (bitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT sawtoothToTriangle
+    GENERIC (
+        bitNb : positive := 16
+    );
+    PORT (
+        triangle : OUT    unsigned (bitNb-1 DOWNTO 0);
+        sawtooth : IN     unsigned (bitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom;
+    FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients;
+    FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister;
+    FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger;
+    FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned;
+    FOR ALL : resizer USE ENTITY SplineInterpolator.resizer;
+    FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
+    FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
+    FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
+    FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable;
+    -- pragma synthesis_on
+
+
+BEGIN
+    -- Architecture concurrent statements
+    -- HDL Embedded Text Block 2 eb2
+    logic1 <= '1';
+
+    -- HDL Embedded Text Block 3 eb3
+    logic0 <= '0';
+
+
+    -- Instance port mappings.
+    I_spline : interpolatorCalculatePolynom
+        GENERIC MAP (
+            signalBitNb       => signalBitNb,
+            coeffBitNb        => coeffBitNb,
+            oversamplingBitNb => sampleCountBitNb
+        )
+        PORT MAP (
+            clock          => clock,
+            reset          => reset,
+            restartPolynom => newPolynom,
+            d              => d,
+            sampleOut      => sineSigned,
+            c              => c,
+            b              => b,
+            a              => a,
+            en             => logic1
+        );
+    I_coeffs : interpolatorCoefficients
+        GENERIC MAP (
+            bitNb      => signalBitNb,
+            coeffBitNb => coeffBitNb
+        )
+        PORT MAP (
+            sample1           => sample1,
+            sample2           => sample2,
+            sample3           => sample3,
+            sample4           => sample4,
+            a                 => a,
+            b                 => b,
+            c                 => c,
+            d                 => d,
+            interpolateLinear => logic0
+        );
+    I_shReg : interpolatorShiftRegister
+        GENERIC MAP (
+            signalBitNb => signalBitNb
+        )
+        PORT MAP (
+            clock        => clock,
+            reset        => reset,
+            shiftSamples => newPolynom,
+            sampleIn     => sineSamples,
+            sample1      => sample1,
+            sample2      => sample2,
+            sample3      => sample3,
+            sample4      => sample4
+        );
+    I_trig : interpolatorTrigger
+        GENERIC MAP (
+            counterBitNb => sampleCountBitNb
+        )
+        PORT MAP (
+            triggerOut => newPolynom,
+            clock      => clock,
+            reset      => reset,
+            en         => logic1
+        );
+    I_unsigned : offsetToUnsigned
+        GENERIC MAP (
+            bitNb => signalBitNb
+        )
+        PORT MAP (
+            unsignedOut => sine,
+            signedIn    => sineSigned
+        );
+    I_size : resizer
+        GENERIC MAP (
+            inputBitNb  => phaseBitNb,
+            outputBitNb => signalBitNb
+        )
+        PORT MAP (
+            resizeOut => sawtooth_internal,
+            resizeIn  => phase
+        );
+    I_sin : sineTable
+        GENERIC MAP (
+            inputBitNb        => phaseBitNb,
+            outputBitNb       => signalBitNb,
+            tableAddressBitNb => tableAddressBitNb
+        )
+        PORT MAP (
+            sine  => sineSamples,
+            phase => phase
+        );
+    I_saw : sawtoothGen
+        GENERIC MAP (
+            bitNb => phaseBitNb
+        )
+        PORT MAP (
+            sawtooth => phase,
+            clock    => clock,
+            reset    => reset,
+            step     => step,
+            en       => logic1
+        );
+    I_square : sawtoothToSquare
+        GENERIC MAP (
+            bitNb => signalBitNb
+        )
+        PORT MAP (
+            square   => square,
+            sawtooth => sawtooth_internal
+        );
+    I_tri : sawtoothToTriangle
+        GENERIC MAP (
+            bitNb => signalBitNb
+        )
+        PORT MAP (
+            triangle => triangle,
+            sawtooth => sawtooth_internal
+        );
+
+    -- Implicit buffered output assignments
+    sawtooth <= sawtooth_internal;
+
+END struct;

02-SplineInterpolator/SplineInterpolator/hdl/sinetable_entity.vhg

@@ -0,0 +1,27 @@
+-- VHDL Entity SplineInterpolator.sineTable.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:46 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY sineTable IS
+    GENERIC( 
+        inputBitNb        : positive := 16;
+        outputBitNb       : positive := 16;
+        tableAddressBitNb : positive := 3
+    );
+    PORT( 
+        sine  : OUT    signed (outputBitNb-1 DOWNTO 0);
+        phase : IN     unsigned (inputBitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END sineTable ;
+

02-SplineInterpolator/SplineInterpolator/hds/.xrf/interpolatorcalculatepolynom_entity.xrf

@@ -0,0 +1,42 @@
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 83,0 19 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 89,0 20 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 94,0 21 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 104,0 22 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 109,0 23 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 125,0 24 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 130,0 25 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 135,0 26 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 141,0 27 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 1,0 30 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 1,0 31 0 

02-SplineInterpolator/SplineInterpolator/hds/.xrf/interpolatorcoefficients_entity.xrf

@@ -0,0 +1,42 @@
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 104,0 18 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 109,0 19 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 114,0 20 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 119,0 21 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 125,0 22 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 130,0 23 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 140,0 24 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 135,0 25 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 149,0 26 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 1,0 29 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 1,0 30 0 

02-SplineInterpolator/SplineInterpolator/hds/.xrf/interpolatorshiftregister_entity.xrf

@@ -0,0 +1,39 @@
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 83,0 17 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 89,0 18 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 94,0 19 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 99,0 20 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 104,0 21 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 109,0 22 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 114,0 23 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 119,0 24 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 1,0 27 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 1,0 28 0 

02-SplineInterpolator/SplineInterpolator/hds/.xrf/interpolatortrigger_entity.xrf

@@ -0,0 +1,27 @@
+DESIGN interpolator@trigger
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 57,0 17 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 83,0 18 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 89,0 19 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 94,0 20 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 1,0 23 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 1,0 24 0 

02-SplineInterpolator/SplineInterpolator/hds/.xrf/offsettounsigned_entity.xrf

@@ -0,0 +1,21 @@
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 57,0 17 0 
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 83,0 18 0 
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 1,0 21 0 
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 1,0 22 0 

02-SplineInterpolator/SplineInterpolator/hds/.xrf/resizer_entity.xrf

@@ -0,0 +1,21 @@
+DESIGN resizer
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 57,0 18 0 
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 83,0 19 0 
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 1,0 22 0 
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 1,0 23 0 

02-SplineInterpolator/SplineInterpolator/hds/.xrf/sinegen_entity.xrf

@@ -0,0 +1,36 @@
+DESIGN sine@gen
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 52,0 18 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 88,0 19 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 128,0 20 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 98,0 21 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 103,0 22 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 108,0 23 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 118,0 24 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 1,0 27 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 1,0 28 0 

02-SplineInterpolator/SplineInterpolator/hds/.xrf/sinegen_struct.xrf

@@ -0,0 +1,519 @@
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 84,0 9 0 
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 12
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 0,0 16 2 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1,0 19 0 
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 19
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1701,0 24 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1709,0 25 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1717,0 26 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1725,0 27 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2579,0 28 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2447,0 29 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1658,0 30 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 726,0 31 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1277,0 32 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1285,0 33 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1293,0 34 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1301,0 35 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1102,0 36 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2227,0 37 0 
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 38
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 887,0 40 0 
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 42
+LIBRARY SplineInterpolator
+DESIGN interpolator@calculate@polynom
+VIEW student@version
+GRAPHIC 3829,0 44 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 14,0 45 1 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 83,0 51 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 89,0 52 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 94,0 53 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 104,0 54 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 109,0 55 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 125,0 56 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 130,0 57 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 135,0 58 0 
+DESIGN interpolator@calculate@polynom
+VIEW symbol.sb
+GRAPHIC 141,0 59 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3784,0 62 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 14,0 63 1 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 104,0 68 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 109,0 69 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 114,0 70 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 119,0 71 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 125,0 72 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 130,0 73 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 140,0 74 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 135,0 75 0 
+DESIGN interpolator@coefficients
+VIEW symbol.sb
+GRAPHIC 149,0 76 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3739,0 79 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 14,0 80 1 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 83,0 84 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 89,0 85 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 94,0 86 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 99,0 87 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 104,0 88 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 109,0 89 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 114,0 90 0 
+DESIGN interpolator@shift@register
+VIEW symbol.sb
+GRAPHIC 119,0 91 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3698,0 94 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 14,0 95 1 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 57,0 99 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 83,0 100 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 89,0 101 0 
+DESIGN interpolator@trigger
+VIEW symbol.sb
+GRAPHIC 94,0 102 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3846,0 105 0 
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 14,0 106 1 
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 57,0 110 0 
+DESIGN offset@to@unsigned
+VIEW symbol.sb
+GRAPHIC 83,0 111 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3584,0 114 0 
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 14,0 115 1 
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 57,0 120 0 
+DESIGN resizer
+VIEW symbol.sb
+GRAPHIC 83,0 121 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3601,0 124 0 
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 14,0 125 1 
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 57,0 131 0 
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 83,0 132 0 
+LIBRARY WaveformGenerator
+DESIGN sawtooth@gen
+VIEW student@version
+GRAPHIC 3673,0 135 0 
+DESIGN sawtooth@gen
+VIEW symbol.sb
+GRAPHIC 14,0 136 1 
+DESIGN sawtooth@gen
+VIEW symbol.sb
+GRAPHIC 57,0 140 0 
+DESIGN sawtooth@gen
+VIEW symbol.sb
+GRAPHIC 52,0 141 0 
+DESIGN sawtooth@gen
+VIEW symbol.sb
+GRAPHIC 76,0 142 0 
+DESIGN sawtooth@gen
+VIEW symbol.sb
+GRAPHIC 83,0 143 0 
+DESIGN sawtooth@gen
+VIEW symbol.sb
+GRAPHIC 89,0 144 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2908,0 147 0 
+DESIGN sawtooth@to@square
+VIEW symbol.sb
+GRAPHIC 14,0 148 1 
+DESIGN sawtooth@to@square
+VIEW symbol.sb
+GRAPHIC 57,0 152 0 
+DESIGN sawtooth@to@square
+VIEW symbol.sb
+GRAPHIC 83,0 153 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2925,0 156 0 
+DESIGN sawtooth@to@triangle
+VIEW symbol.sb
+GRAPHIC 14,0 157 1 
+DESIGN sawtooth@to@triangle
+VIEW symbol.sb
+GRAPHIC 57,0 161 0 
+DESIGN sawtooth@to@triangle
+VIEW symbol.sb
+GRAPHIC 83,0 162 0 
+LIBRARY SplineInterpolator
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 165
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3829,0 168 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3784,0 169 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3739,0 170 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3698,0 171 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3846,0 172 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3584,0 173 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3673,0 174 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2908,0 175 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2925,0 176 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3601,0 177 0 
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 180
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2375,0 183 0 
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 185
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2562,0 186 0 
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 188
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 189
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3829,0 191 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3836,0 192 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1814,0 198 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1822,0 199 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1830,0 200 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1727,0 201 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2219,0 202 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1719,0 203 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1711,0 204 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1703,0 205 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2394,0 206 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3784,0 208 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3791,0 209 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1279,0 214 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1287,0 215 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1295,0 216 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1303,0 217 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1703,0 218 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1711,0 219 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1719,0 220 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1727,0 221 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2571,0 222 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3739,0 224 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3746,0 225 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1228,0 229 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1220,0 230 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1106,0 231 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1096,0 232 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1279,0 233 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1287,0 234 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1295,0 235 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1303,0 236 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3698,0 238 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3705,0 239 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1106,0 243 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 985,0 244 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 993,0 245 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2386,0 246 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3846,0 248 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3853,0 249 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 562,0 253 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2219,0 254 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3584,0 256 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3591,0 257 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 601,0 262 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 414,0 263 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3601,0 265 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3608,0 266 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 1096,0 272 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 472,0 273 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3673,0 275 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 3680,0 276 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 414,0 280 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 15,0 281 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 237,0 282 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 781,0 283 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2449,0 284 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2908,0 286 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2915,0 287 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 480,0 291 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 887,0 292 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2925,0 294 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 2932,0 295 1 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 424,0 299 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 858,0 300 0 
+DESIGN sine@gen
+VIEW struct.bd
+GRAPHIC 887,0 304 0 
+DESIGN sine@gen
+VIEW struct.bd
+NO_GRAPHIC 306

02-SplineInterpolator/SplineInterpolator/hds/.xrf/sinetable_entity.xrf

@@ -0,0 +1,21 @@
+DESIGN sine@table
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 57,0 19 0 
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 83,0 20 0 
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 1,0 23 0 
+DESIGN sine@table
+VIEW symbol.sb
+GRAPHIC 1,0 24 0 

02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity SplineInterpolator_test.sineGen_tb.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:04 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY sineGen_tb IS
+-- Declarations
+
+END sineGen_tb ;
+

02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_struct.vhg

@@ -0,0 +1,108 @@
+--
+-- VHDL Architecture SplineInterpolator_test.sineGen_tb.struct
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:41:39 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY SplineInterpolator;
+LIBRARY SplineInterpolator_test;
+
+ARCHITECTURE struct OF sineGen_tb IS
+
+    -- Architecture declarations
+    constant signalBitNb: positive := 16;
+    constant phaseBitNb: positive := 10;
+    constant clockFrequency: real := 60.0E6;
+    --constant clockFrequency: real := 66.0E6;
+
+    -- Internal signal declarations
+    SIGNAL clock    : std_ulogic;
+    SIGNAL reset    : std_ulogic;
+    SIGNAL sawtooth : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL sine     : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL square   : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL step     : unsigned(phaseBitNb-1 DOWNTO 0);
+    SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);
+
+
+    -- Component Declarations
+    COMPONENT sineGen
+    GENERIC (
+        signalBitNb : positive := 16;
+        phaseBitNb  : positive := 10
+    );
+    PORT (
+        clock    : IN     std_ulogic ;
+        reset    : IN     std_ulogic ;
+        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
+        sawtooth : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT sineGen_tester
+    GENERIC (
+        signalBitNb    : positive := 16;
+        phaseBitNb     : positive := 10;
+        clockFrequency : real     := 60.0E6
+    );
+    PORT (
+        sawtooth : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        square   : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        clock    : OUT    std_ulogic ;
+        reset    : OUT    std_ulogic ;
+        step     : OUT    unsigned (phaseBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
+    FOR ALL : sineGen_tester USE ENTITY SplineInterpolator_test.sineGen_tester;
+    -- pragma synthesis_on
+
+
+BEGIN
+
+    -- Instance port mappings.
+    I_DUT : sineGen
+        GENERIC MAP (
+            signalBitNb => signalBitNb,
+            phaseBitNb  => phaseBitNb
+        )
+        PORT MAP (
+            clock    => clock,
+            reset    => reset,
+            step     => step,
+            sawtooth => sawtooth,
+            sine     => sine,
+            square   => square,
+            triangle => triangle
+        );
+    I_tb : sineGen_tester
+        GENERIC MAP (
+            signalBitNb    => signalBitNb,
+            phaseBitNb     => phaseBitNb,
+            clockFrequency => clockFrequency
+        )
+        PORT MAP (
+            sawtooth => sawtooth,
+            sine     => sine,
+            square   => square,
+            triangle => triangle,
+            clock    => clock,
+            reset    => reset,
+            step     => step
+        );
+
+END struct;

02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tester_entity.vhg

@@ -0,0 +1,32 @@
+-- VHDL Entity SplineInterpolator_test.sineGen_tester.interface
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:41:39 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+ENTITY sineGen_tester IS
+    GENERIC( 
+        signalBitNb    : positive := 16;
+        phaseBitNb     : positive := 10;
+        clockFrequency : real     := 60.0E6
+    );
+    PORT( 
+        sawtooth : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        square   : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        clock    : OUT    std_ulogic;
+        reset    : OUT    std_ulogic;
+        step     : OUT    unsigned (phaseBitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END sineGen_tester ;
+

02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN sine@gen_tb
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN sine@gen_tb
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN sine@gen_tb
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN sine@gen_tb
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_struct.xrf

@@ -0,0 +1,153 @@
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 142,0 9 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 12
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 0,0 16 2 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 1,0 19 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 19
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 53,0 25 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 45,0 26 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 933,0 27 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 909,0 28 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 925,0 29 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 996,0 30 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 917,0 31 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 32
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 33
+LIBRARY SplineInterpolator
+DESIGN sine@gen
+VIEW struct
+GRAPHIC 1519,0 35 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 14,0 36 1 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 52,0 41 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 88,0 42 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 128,0 43 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 98,0 44 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 103,0 45 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 108,0 46 0 
+DESIGN sine@gen
+VIEW symbol.sb
+GRAPHIC 118,0 47 0 
+LIBRARY SplineInterpolator_test
+DESIGN sine@gen_tester
+VIEW test
+GRAPHIC 421,0 50 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 14,0 51 1 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 935,0 57 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 911,0 58 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 927,0 59 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 919,0 60 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 55,0 61 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 47,0 62 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 998,0 63 0 
+LIBRARY SplineInterpolator_test
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 66
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 1519,0 69 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 421,0 70 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 73
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 75
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 1519,0 77 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 1526,0 78 1 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 55,0 83 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 47,0 84 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 998,0 85 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 935,0 86 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 911,0 87 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 927,0 88 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 919,0 89 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 421,0 91 0 
+DESIGN sine@gen_tb
+VIEW struct.bd
+GRAPHIC 428,0 92 1 
+DESIGN sine@gen_tb
+VIEW struct.bd
+NO_GRAPHIC 107

02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tester_entity.xrf

@@ -0,0 +1,36 @@
+DESIGN sine@gen_tester
+VIEW interface
+NO_GRAPHIC 0
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 50,0 8 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 13,0 13 1 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 409,0 19 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 414,0 20 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 419,0 21 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 429,0 22 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 399,0 23 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 404,0 24 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 424,0 25 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 1,0 28 0 
+DESIGN sine@gen_tester
+VIEW interface
+GRAPHIC 1,0 29 0