add resize + tabel

02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tester_entity.vhg

@@ -0,0 +1,32 @@
+-- VHDL Entity SplineInterpolator_test.sineGen_tester.interface
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:41:39 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+ENTITY sineGen_tester IS
+    GENERIC( 
+        signalBitNb    : positive := 16;
+        phaseBitNb     : positive := 10;
+        clockFrequency : real     := 60.0E6
+    );
+    PORT( 
+        sawtooth : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        square   : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        clock    : OUT    std_ulogic;
+        reset    : OUT    std_ulogic;
+        step     : OUT    unsigned (phaseBitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END sineGen_tester ;
+