add resize + tabel

02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity SplineInterpolator_test.sineGen_tb.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:00:04 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY sineGen_tb IS
+-- Declarations
+
+END sineGen_tb ;
+