add resize + tabel

02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd

@@ -1,15 +1,25 @@
 ARCHITECTURE studentVersion OF sineTable IS
 
   signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
+  signal phaseTableAddress2 : unsigned(tableAddressBitNb-1 downto 0);
   signal quarterSine : signed(sine'range);
 
 BEGIN
 
   phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
 
-  quarterTable: process(phaseTableAddress)
+  sequenceTable: process(phase)
   begin
-    case to_integer(phaseTableAddress) is
+    if phase(phase'high-1) = '1' then
+      phaseTableAddress2 <= 8 - phaseTableAddress;
+    else
+      phaseTableAddress2 <= phaseTableAddress;
+    end if;
+  end process sequenceTable;
+
+  quarterTable: process(phaseTableAddress2)
+  begin
+    case to_integer(phaseTableAddress2) is
       when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
       when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
       when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
@@ -22,6 +32,15 @@ BEGIN
     end case;
   end process quarterTable;
 
-  sine <= (others => '0');
+  invert: process(quarterSine)
+  begin
+    if phase(phase'high) = '1' then
+      sine <= NOT quarterSine;
+    else
+      sine <= quarterSine;
+    end if;
+  end process invert;
+  
+  --sine <= quarterSine;
 
 END ARCHITECTURE studentVersion;