add resize + tabel
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		| @@ -1,4 +1,24 @@ | ||||
| ARCHITECTURE studentVersion OF resizer IS | ||||
|  | ||||
| 	signal mySignal : unsigned(outputBitNb-1 downto 0); | ||||
| 	 | ||||
| -------------------------------------------------------------------------------- | ||||
| BEGIN | ||||
|   resizeOut <= (others => '0'); | ||||
|  | ||||
| INPUT_BIGGER: if inputBitNb >= outputBitNb generate | ||||
| 	process(resizeIn) | ||||
| 	begin | ||||
| 		mySignal <= resize(shift_right(resizeIn, inputBitNb - outputBitNb), outputBitNb); | ||||
| 	end process; | ||||
| end generate INPUT_BIGGER; | ||||
|  | ||||
| OUTPUT_BIGGER: if inputBitNb <= outputBitNb generate | ||||
| 	process(resizeIn) | ||||
| 	begin | ||||
| 		mySignal <= shift_left(resize(resizeIn, outputBitNb), outputBitNb - inputBitNb); | ||||
| 	end process; | ||||
| end generate OUTPUT_BIGGER; | ||||
|  | ||||
| 	resizeOut <= mySignal; | ||||
|  | ||||
| END ARCHITECTURE studentVersion; | ||||
|   | ||||
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