some file i don't know if needed

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_entity.vhg

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+-- VHDL Entity AhbLiteComponents_test.ahbUart_tb.symbol
+--
+-- Created:
+--          by - zas.UNKNOWN (ZELL)
+--          at - 17:08:42 02/17/2020
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY ahbUart_tb IS
+-- Declarations
+
+END ahbUart_tb ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_struct.vhg

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+--
+-- VHDL Architecture AhbLiteComponents_test.ahbUart_tb.struct
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 15:07:00 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+LIBRARY AhbLiteComponents;
+LIBRARY AhbLiteComponents_test;
+
+ARCHITECTURE struct OF ahbUart_tb IS
+
+    -- Architecture declarations
+    constant txFifoDepth: positive := 1;
+    constant rxFifoDepth: positive := 1;
+    
+    constant clockFrequency : real := 60.0E6;
+    --constant clockFrequency : real := 66.0E6;
+
+    -- Internal signal declarations
+    SIGNAL RxD      : std_ulogic;
+    SIGNAL TxD      : std_ulogic;
+    SIGNAL hAddr    : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
+    SIGNAL hClk     : std_uLogic;
+    SIGNAL hRData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
+    SIGNAL hReady   : std_uLogic;
+    SIGNAL hReset_n : std_uLogic;
+    SIGNAL hResp    : std_uLogic;
+    SIGNAL hSel     : std_uLogic;
+    SIGNAL hTrans   : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
+    SIGNAL hWData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
+    SIGNAL hWrite   : std_uLogic;
+
+
+    -- Component Declarations
+    COMPONENT ahbUart
+    GENERIC (
+        txFifoDepth : positive := 8;
+        rxFifoDepth : positive := 1
+    );
+    PORT (
+        RxD      : IN     std_ulogic ;
+        hAddr    : IN     unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : IN     std_uLogic ;
+        hReset_n : IN     std_uLogic ;
+        hSel     : IN     std_uLogic ;
+        hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : IN     std_uLogic ;
+        TxD      : OUT    std_ulogic ;
+        hRData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : OUT    std_uLogic ;
+        hResp    : OUT    std_uLogic 
+    );
+    END COMPONENT;
+    COMPONENT ahbUart_tester
+    GENERIC (
+        clockFrequency : real
+    );
+    PORT (
+        TxD      : IN     std_ulogic ;
+        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : IN     std_uLogic ;
+        hResp    : IN     std_uLogic ;
+        RxD      : OUT    std_ulogic ;
+        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : OUT    std_uLogic ;
+        hReset_n : OUT    std_uLogic ;
+        hSel     : OUT    std_uLogic ;
+        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : OUT    std_uLogic 
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : ahbUart USE ENTITY AhbLiteComponents.ahbUart;
+    FOR ALL : ahbUart_tester USE ENTITY AhbLiteComponents_test.ahbUart_tester;
+    -- pragma synthesis_on
+
+
+BEGIN
+
+    -- Instance port mappings.
+    I_DUT : ahbUart
+        GENERIC MAP (
+            txFifoDepth => txFifoDepth,
+            rxFifoDepth => rxFifoDepth
+        )
+        PORT MAP (
+            RxD      => RxD,
+            hAddr    => hAddr,
+            hClk     => hClk,
+            hReset_n => hReset_n,
+            hSel     => hSel,
+            hTrans   => hTrans,
+            hWData   => hWData,
+            hWrite   => hWrite,
+            TxD      => TxD,
+            hRData   => hRData,
+            hReady   => hReady,
+            hResp    => hResp
+        );
+    I_tester : ahbUart_tester
+        GENERIC MAP (
+            clockFrequency => clockFrequency
+        )
+        PORT MAP (
+            TxD      => TxD,
+            hRData   => hRData,
+            hReady   => hReady,
+            hResp    => hResp,
+            RxD      => RxD,
+            hAddr    => hAddr,
+            hClk     => hClk,
+            hReset_n => hReset_n,
+            hSel     => hSel,
+            hTrans   => hTrans,
+            hWData   => hWData,
+            hWrite   => hWrite
+        );
+
+END struct;

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tester_entity.vhg

@@ -0,0 +1,37 @@
+-- VHDL Entity AhbLiteComponents_test.ahbUart_tester.interface
+--
+-- Created:
+--          by - zas.UNKNOWN (ZELL)
+--          at - 17:08:42 02/17/2020
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+ENTITY ahbUart_tester IS
+    GENERIC( 
+        clockFrequency : real
+    );
+    PORT( 
+        TxD      : IN     std_ulogic;
+        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : IN     std_uLogic;
+        hResp    : IN     std_uLogic;
+        RxD      : OUT    std_ulogic;
+        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : OUT    std_uLogic;
+        hReset_n : OUT    std_uLogic;
+        hSel     : OUT    std_uLogic;
+        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : OUT    std_uLogic
+    );
+
+-- Declarations
+
+END ahbUart_tester ;
+