some file i don't know if needed
This commit is contained in:
		| @@ -0,0 +1,38 @@ | ||||
| -- VHDL Entity AhbLiteComponents.ahbUart.symbol | ||||
| -- | ||||
| -- Created: | ||||
| --          by - remi.heredero.UNKNOWN (WE2330808) | ||||
| --          at - 15:08:33 23.02.2024 | ||||
| -- | ||||
| -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) | ||||
| -- | ||||
| LIBRARY ieee; | ||||
|   USE ieee.std_logic_1164.all; | ||||
|   USE ieee.numeric_std.all; | ||||
| LIBRARY AhbLite; | ||||
|   USE AhbLite.ahbLite.all; | ||||
|  | ||||
| ENTITY ahbUart IS | ||||
|     GENERIC(  | ||||
|         txFifoDepth : positive := 8; | ||||
|         rxFifoDepth : positive := 1 | ||||
|     ); | ||||
|     PORT(  | ||||
|         RxD      : IN     std_ulogic; | ||||
|         hAddr    : IN     unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); | ||||
|         hClk     : IN     std_uLogic; | ||||
|         hReset_n : IN     std_uLogic; | ||||
|         hSel     : IN     std_uLogic; | ||||
|         hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); | ||||
|         hWData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); | ||||
|         hWrite   : IN     std_uLogic; | ||||
|         TxD      : OUT    std_ulogic; | ||||
|         hRData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); | ||||
|         hReady   : OUT    std_uLogic; | ||||
|         hResp    : OUT    std_uLogic | ||||
|     ); | ||||
|  | ||||
| -- Declarations | ||||
|  | ||||
| END ahbUart ; | ||||
|  | ||||
		Reference in New Issue
	
	Block a user