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split polygon in 2 process

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This commit is contained in:
Rémi Heredero
2024-03-01 14:53:57 +01:00
parent 27e755cc2f
commit 0233d8b730
10 changed files with 579 additions and 398 deletions
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7
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg
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@@ -3,7 +3,7 @@
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 13:13:41 01.03.2024
-- at - 14:26:40 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@@ -29,6 +29,7 @@ ARCHITECTURE struct OF waveformGen_tb IS
SIGNAL polygon : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL reset : std_ulogic;
SIGNAL sawtooth : unsigned(phaseBitNb-1 DOWNTO 0);
SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL step : unsigned(bitNb-1 DOWNTO 0);
SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);
@@ -62,6 +63,7 @@ ARCHITECTURE struct OF waveformGen_tb IS
PORT (
polygon : IN unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0);
sine : IN unsigned (signalBitNb-1 DOWNTO 0);
square : IN unsigned (signalBitNb-1 DOWNTO 0);
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : OUT std_ulogic ;
@@ -93,7 +95,7 @@ BEGIN
step => step,
polygon => polygon,
sawtooth => sawtooth,
sine => OPEN,
sine => sine,
square => square,
triangle => triangle
);
@@ -105,6 +107,7 @@ BEGIN
PORT MAP (
polygon => polygon,
sawtooth => sawtooth,
sine => sine,
square => square,
triangle => triangle,
clock => clock,

3
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg
View File

@@ -2,7 +2,7 @@
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 13:12:24 01.03.2024
-- at - 14:26:40 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@@ -20,6 +20,7 @@ ENTITY waveformGen_tester IS
PORT(
polygon : IN unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0);
sine : IN unsigned (signalBitNb-1 DOWNTO 0);
square : IN unsigned (signalBitNb-1 DOWNTO 0);
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : OUT std_ulogic;