DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
itemName "ALL"
)
]
instances [
(Instance
name "I_tester"
duLibraryName "SystemOnChip_test"
duName "beamerSoc_tester"
elements [
(GiElement
name "ioNb"
type "positive"
value "ioNb"
)
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "clockFrequency"
type "real"
value "clockFrequency"
)
]
mwi 0
uid 1616,0
)
(Instance
name "I_filt"
duLibraryName "WaveformGenerator"
duName "lowpass"
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "shiftBitNb"
type "positive"
value "lowpassShiftBitNb"
)
]
mwi 0
uid 2852,0
)
(Instance
name "I_DUT"
duLibraryName "SystemOnChip"
duName "beamerSoc"
elements [
(GiElement
name "ioNb"
type "positive"
value "ioNb"
)
(GiElement
name "testOutBitNb"
type "positive"
value "testOutBitNb"
)
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
mwi 0
uid 3413,0
)
]
embeddedInstances [
(EmbeddedInstance
name "eb1"
number "1"
)
(EmbeddedInstance
name "eb3"
number "3"
)
]
libraryRefs [
"ieee"
]
)
version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "asm_file"
value "beamer.asm"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tb"
)
(vvPair
variable "d_logical"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerSoc_tb"
)
(vvPair
variable "date"
value "28.04.2023"
)
(vvPair
variable "day"
value "ven."
)
(vvPair
variable "day_long"
value "vendredi"
)
(vvPair
variable "dd"
value "28"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "beamerSoc_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "axel.amand"
)
(vvPair
variable "graphical_source_date"
value "28.04.2023"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE7860"
)
(vvPair
variable "graphical_source_time"
value "15:06:16"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE7860"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "SystemOnChip_test"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/SystemOnChip_test"
)
(vvPair
variable "mm"
value "04"
)
(vvPair
variable "module_name"
value "beamerSoc_tb"
)
(vvPair
variable "month"
value "avr."
)
(vvPair
variable "month_long"
value "avril"
)
(vvPair
variable "p"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerSoc_tb\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_AsmPath"
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$ISE_WORK_DIR"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME/modeltech/bin"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "15:06:16"
)
(vvPair
variable "unit"
value "beamerSoc_tb"
)
(vvPair
variable "user"
value "axel.amand"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2023"
)
(vvPair
variable "yy"
value "23"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 153,0
optionalChildren [
*1 (Grouping
uid 110,0
optionalChildren [
*2 (CommentText
uid 112,0
shape (Rectangle
uid 113,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "72000,73000,89000,74000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 114,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "72200,73500,72200,73500"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*3 (CommentText
uid 115,0
shape (Rectangle
uid 116,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,69000,93000,70000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 117,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "89200,69500,89200,69500"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*4 (CommentText
uid 118,0
shape (Rectangle
uid 119,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "72000,71000,89000,72000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 120,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "72200,71500,72200,71500"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*5 (CommentText
uid 121,0
shape (Rectangle
uid 122,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "68000,71000,72000,72000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 123,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "68200,71500,68200,71500"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*6 (CommentText
uid 124,0
shape (Rectangle
uid 125,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,70000,109000,74000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 126,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "89200,70200,103300,71400"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
)
*7 (CommentText
uid 127,0
shape (Rectangle
uid 128,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "93000,69000,109000,70000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 129,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "93200,69500,93200,69500"
st "
<enter project name here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
)
*8 (CommentText
uid 130,0
shape (Rectangle
uid 131,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "68000,69000,89000,71000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 132,0
va (VaSet
fg "32768,0,0"
)
xt "73350,69400,83650,70600"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
)
*9 (CommentText
uid 133,0
shape (Rectangle
uid 134,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "68000,72000,72000,73000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 135,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "68200,72500,68200,72500"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*10 (CommentText
uid 136,0
shape (Rectangle
uid 137,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "68000,73000,72000,74000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 138,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "68200,73500,68200,73500"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*11 (CommentText
uid 139,0
shape (Rectangle
uid 140,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "72000,72000,89000,73000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 141,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "72200,72500,72200,72500"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
uid 111,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "68000,69000,109000,74000"
)
oxt "14000,66000,55000,71000"
)
*12 (Blk
uid 1616,0
shape (Rectangle
uid 1617,0
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "19000,58000,101000,66000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1618,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*13 (Text
uid 1619,0
va (VaSet
)
xt "18600,66200,30200,67400"
st "SystemOnChip_test"
blo "18600,67200"
tm "BdLibraryNameMgr"
)
*14 (Text
uid 1620,0
va (VaSet
)
xt "18600,67400,29200,68600"
st "beamerSoc_tester"
blo "18600,68400"
tm "BlkNameMgr"
)
*15 (Text
uid 1621,0
va (VaSet
)
xt "18600,68600,23400,69800"
st "I_tester"
blo "18600,69600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1622,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1623,0
text (MLText
uid 1624,0
va (VaSet
)
xt "19000,70000,45200,73600"
st "ioNb           = ioNb              ( positive )  
signalBitNb    = signalBitNb       ( positive )  
clockFrequency = clockFrequency    ( real     )  
"
)
header ""
)
elements [
(GiElement
name "ioNb"
type "positive"
value "ioNb"
)
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "clockFrequency"
type "real"
value "clockFrequency"
)
]
)
)
*16 (Net
uid 2464,0
decl (Decl
n "reset"
t "std_ulogic"
o 12
suid 18,0
)
declText (MLText
uid 2465,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,31400,15500,32400"
st "SIGNAL reset       : std_ulogic
"
)
)
*17 (Net
uid 2472,0
decl (Decl
n "clock"
t "std_ulogic"
o 3
suid 19,0
)
declText (MLText
uid 2473,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,21200,15500,22200"
st "SIGNAL clock       : std_ulogic
"
)
)
*18 (Net
uid 2480,0
decl (Decl
n "RxD"
t "std_ulogic"
o 1
suid 20,0
)
declText (MLText
uid 2481,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,19200,15800,20200"
st "SIGNAL RxD         : std_ulogic
"
)
)
*19 (Net
uid 2488,0
decl (Decl
n "TxD"
t "std_ulogic"
o 2
suid 21,0
)
declText (MLText
uid 2489,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,20200,15700,21200"
st "SIGNAL TxD         : std_ulogic
"
)
)
*20 (Net
uid 2496,0
decl (Decl
n "selSinCos"
t "std_ulogic"
o 13
suid 22,0
)
declText (MLText
uid 2497,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,32400,16100,33400"
st "SIGNAL selSinCos   : std_ulogic
"
)
)
*21 (Net
uid 2504,0
decl (Decl
n "outY"
t "std_ulogic"
o 11
suid 23,0
)
declText (MLText
uid 2505,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,30400,15600,31400"
st "SIGNAL outY        : std_ulogic
"
)
)
*22 (Net
uid 2512,0
decl (Decl
n "outX"
t "std_ulogic"
o 10
suid 24,0
)
declText (MLText
uid 2513,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,29400,15600,30400"
st "SIGNAL outX        : std_ulogic
"
)
)
*23 (HdlText
uid 2542,0
optionalChildren [
*24 (EmbeddedText
uid 2548,0
commentText (CommentText
uid 2549,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 2550,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "69000,31000,85000,41000"
)
oxt "0,0,18000,5000"
text (MLText
uid 2551,0
va (VaSet
)
xt "69200,31200,84200,40800"
st "
tristate: process(ioEn, ioOut)
begin
  for index in io'range loop
    if ioEn(index) = '1' then
      io(index) <= ioOut(index);
    else
      io(index) <= 'Z';
    end if;
  end loop;
end process tristate;

ioIn <= std_ulogic_vector(io);

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 2543,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "69000,30000,85000,42000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 2544,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*25 (Text
uid 2545,0
va (VaSet
font "Verdana,8,1"
)
xt "68850,42000,71150,43000"
st "eb1"
blo "68850,42800"
tm "HdlTextNameMgr"
)
*26 (Text
uid 2546,0
va (VaSet
font "Verdana,8,1"
)
xt "68850,43000,70050,44000"
st "1"
blo "68850,43800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 2547,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "69250,40250,70750,41750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*27 (Net
uid 2584,0
decl (Decl
n "io"
t "std_logic_vector"
b "(ioNb-1 DOWNTO 0)"
o 4
suid 26,0
)
declText (MLText
uid 2585,0
va (VaSet
)
xt "2000,22200,32900,23400"
st "SIGNAL io          : std_logic_vector(ioNb-1 DOWNTO 0)
"
)
)
*28 (Net
uid 2586,0
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 6
suid 27,0
)
declText (MLText
uid 2587,0
va (VaSet
)
xt "2000,24600,34000,25800"
st "SIGNAL ioIn        : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
)
)
*29 (Net
uid 2588,0
decl (Decl
n "ioOut"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 7
suid 28,0
)
declText (MLText
uid 2589,0
va (VaSet
)
xt "2000,25800,34500,27000"
st "SIGNAL ioOut       : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
)
)
*30 (Net
uid 2590,0
decl (Decl
n "ioEn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 5
suid 29,0
)
declText (MLText
uid 2591,0
va (VaSet
)
xt "2000,23400,34200,24600"
st "SIGNAL ioEn        : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
)
)
*31 (HdlText
uid 2843,0
optionalChildren [
*32 (EmbeddedText
uid 2848,0
commentText (CommentText
uid 2849,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 2850,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "45000,13000,61000,15000"
)
oxt "0,0,18000,5000"
text (MLText
uid 2851,0
va (VaSet
)
xt "45200,13200,60700,14400"
st "
lowpassInY <= (others => outY);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 2844,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "45000,12000,61000,16000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 2845,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*33 (Text
uid 2846,0
va (VaSet
)
xt "45400,16000,48000,17200"
st "eb3"
blo "45400,17000"
tm "HdlTextNameMgr"
)
*34 (Text
uid 2847,0
va (VaSet
)
xt "45400,17000,46800,18200"
st "3"
blo "45400,18000"
tm "HdlTextNumberMgr"
)
]
)
)
*35 (SaComponent
uid 2852,0
optionalChildren [
*36 (CptPort
uid 2861,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2862,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,17625,69000,18375"
)
tg (CPTG
uid 2863,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2864,0
va (VaSet
)
xt "70000,17400,73400,18600"
st "clock"
blo "70000,18400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*37 (CptPort
uid 2865,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2866,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "85000,13625,85750,14375"
)
tg (CPTG
uid 2867,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2868,0
va (VaSet
)
xt "76700,13400,84000,14600"
st "lowpassOut"
ju 2
blo "84000,14400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "lowpassOut"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 1
)
)
)
*38 (CptPort
uid 2869,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2870,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,19625,69000,20375"
)
tg (CPTG
uid 2871,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2872,0
va (VaSet
)
xt "70000,19400,73300,20600"
st "reset"
blo "70000,20400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*39 (CptPort
uid 2873,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2874,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,13625,69000,14375"
)
tg (CPTG
uid 2875,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2876,0
va (VaSet
)
xt "70000,13400,75800,14600"
st "lowpassIn"
blo "70000,14400"
)
)
thePort (LogicalPort
decl (Decl
n "lowpassIn"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 4
)
)
)
]
shape (Rectangle
uid 2853,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "69000,10000,85000,22000"
)
oxt "32000,10000,48000,22000"
ttg (MlTextGroup
uid 2854,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*40 (Text
uid 2855,0
va (VaSet
font "Verdana,9,1"
)
xt "69600,21800,81100,23000"
st "WaveformGenerator"
blo "69600,22800"
tm "BdLibraryNameMgr"
)
*41 (Text
uid 2856,0
va (VaSet
font "Verdana,9,1"
)
xt "69600,23000,74200,24200"
st "lowpass"
blo "69600,24000"
tm "CptNameMgr"
)
*42 (Text
uid 2857,0
va (VaSet
font "Verdana,9,1"
)
xt "69600,24200,72900,25400"
st "I_filt"
blo "69600,25200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2858,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2859,0
text (MLText
uid 2860,0
va (VaSet
font "Verdana,8,0"
)
xt "69000,25600,89800,27600"
st "signalBitNb = signalBitNb          ( positive )  
shiftBitNb  = lowpassShiftBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "shiftBitNb"
type "positive"
value "lowpassShiftBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*43 (Net
uid 2901,0
decl (Decl
n "lowpassInY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 8
suid 30,0
)
declText (MLText
uid 2902,0
va (VaSet
)
xt "2000,27000,35000,28200"
st "SIGNAL lowpassInY  : unsigned(signalBitNb-1 DOWNTO 0)
"
)
)
*44 (Net
uid 2903,0
decl (Decl
n "lowpassOutY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 9
suid 31,0
)
declText (MLText
uid 2904,0
va (VaSet
)
xt "2000,28200,35500,29400"
st "SIGNAL lowpassOutY : unsigned(signalBitNb-1 DOWNTO 0)
"
)
)
*45 (SaComponent
uid 3413,0
optionalChildren [
*46 (CptPort
uid 3369,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3370,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,45625,37000,46375"
)
tg (CPTG
uid 3371,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3372,0
va (VaSet
)
xt "38000,45400,41400,46600"
st "clock"
blo "38000,46400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 7
suid 1,0
)
)
)
*47 (CptPort
uid 3373,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3374,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "53000,41625,53750,42375"
)
tg (CPTG
uid 3375,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3376,0
va (VaSet
)
xt "49001,41400,52001,42600"
st "outX"
ju 2
blo "52001,42400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outX"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*48 (CptPort
uid 3377,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3378,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "53000,43625,53750,44375"
)
tg (CPTG
uid 3379,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3380,0
va (VaSet
)
xt "49001,43400,52001,44600"
st "outY"
ju 2
blo "52001,44400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outY"
t "std_ulogic"
o 4
suid 5,0
)
)
)
*49 (CptPort
uid 3381,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3382,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "53000,45625,53750,46375"
)
tg (CPTG
uid 3383,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3384,0
va (VaSet
)
xt "46201,45400,52001,46600"
st "selSinCos"
ju 2
blo "52001,46400"
)
)
thePort (LogicalPort
decl (Decl
n "selSinCos"
t "std_ulogic"
o 5
suid 13,0
)
)
)
*50 (CptPort
uid 3385,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3386,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,47625,37000,48375"
)
tg (CPTG
uid 3387,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3388,0
va (VaSet
)
xt "38000,47400,41300,48600"
st "reset"
blo "38000,48400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 6
suid 2017,0
)
)
)
*51 (CptPort
uid 3389,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3390,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,33625,37000,34375"
)
tg (CPTG
uid 3391,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3392,0
va (VaSet
)
xt "38000,33400,40800,34600"
st "TxD"
blo "38000,34400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "TxD"
t "std_ulogic"
o 1
suid 2018,0
)
)
)
*52 (CptPort
uid 3393,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3394,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,35625,37000,36375"
)
tg (CPTG
uid 3395,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3396,0
va (VaSet
)
xt "38000,35400,40800,36600"
st "RxD"
blo "38000,36400"
)
)
thePort (LogicalPort
decl (Decl
n "RxD"
t "std_ulogic"
o 2
suid 2019,0
)
)
)
*53 (CptPort
uid 3397,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3398,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "53000,33625,53750,34375"
)
tg (CPTG
uid 3399,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3400,0
va (VaSet
)
xt "49100,33400,52000,34600"
st "ioEn"
ju 2
blo "52000,34400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ioEn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 8
suid 2020,0
)
)
)
*54 (CptPort
uid 3401,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3402,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "53000,35625,53750,36375"
)
tg (CPTG
uid 3403,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3404,0
va (VaSet
)
xt "48500,35400,52000,36600"
st "ioOut"
ju 2
blo "52000,36400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ioOut"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 9
suid 2021,0
)
)
)
*55 (CptPort
uid 3405,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3406,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "53000,37625,53750,38375"
)
tg (CPTG
uid 3407,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3408,0
va (VaSet
)
xt "49300,37400,52000,38600"
st "ioIn"
ju 2
blo "52000,38400"
)
)
thePort (LogicalPort
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 10
suid 2022,0
)
)
)
*56 (CptPort
uid 3409,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3410,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "44625,29250,45375,30000"
)
tg (CPTG
uid 3411,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3412,0
va (VaSet
)
xt "43000,31000,47600,32200"
st "testOut"
ju 2
blo "47600,32000"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 11
suid 2024,0
)
)
)
]
shape (Rectangle
uid 3414,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "37000,30000,53000,50000"
)
oxt "36000,10000,52000,30000"
ttg (MlTextGroup
uid 3415,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*57 (Text
uid 3416,0
va (VaSet
font "Verdana,9,1"
)
xt "37600,49800,46000,51000"
st "SystemOnChip"
blo "37600,50800"
tm "BdLibraryNameMgr"
)
*58 (Text
uid 3417,0
va (VaSet
font "Verdana,9,1"
)
xt "37600,51000,43600,52200"
st "beamerSoc"
blo "37600,52000"
tm "CptNameMgr"
)
*59 (Text
uid 3418,0
va (VaSet
font "Verdana,9,1"
)
xt "37600,52200,41300,53400"
st "I_DUT"
blo "37600,53200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3419,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3420,0
text (MLText
uid 3421,0
va (VaSet
font "Verdana,8,0"
)
xt "37000,53600,62800,56600"
st "ioNb                = ioNb                   ( positive )  
testOutBitNb        = testOutBitNb           ( positive )  
patternAddressBitNb = patternAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "ioNb"
type "positive"
value "ioNb"
)
(GiElement
name "testOutBitNb"
type "positive"
value "testOutBitNb"
)
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*60 (Wire
uid 2466,0
shape (OrthoPolyLine
uid 2467,0
va (VaSet
vasetType 3
)
xt "35000,48000,36250,58000"
pts [
"36250,48000"
"35000,48000"
"35000,58000"
]
)
start &50
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2470,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2471,0
va (VaSet
font "Verdana,12,0"
)
xt "31250,46600,35350,48000"
st "reset"
blo "31250,47800"
tm "WireNameMgr"
)
)
on &16
)
*61 (Wire
uid 2474,0
shape (OrthoPolyLine
uid 2475,0
va (VaSet
vasetType 3
)
xt "33000,46000,36250,58000"
pts [
"36250,46000"
"33000,46000"
"33000,58000"
]
)
start &46
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2478,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2479,0
va (VaSet
font "Verdana,12,0"
)
xt "31250,44600,35050,46000"
st "clock"
blo "31250,45800"
tm "WireNameMgr"
)
)
on &17
)
*62 (Wire
uid 2482,0
shape (OrthoPolyLine
uid 2483,0
va (VaSet
vasetType 3
)
xt "29000,36000,36250,58000"
pts [
"36250,36000"
"29000,36000"
"29000,58000"
]
)
start &52
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2486,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2487,0
va (VaSet
font "Verdana,12,0"
)
xt "32250,34600,35450,36000"
st "RxD"
blo "32250,35800"
tm "WireNameMgr"
)
)
on &18
)
*63 (Wire
uid 2490,0
shape (OrthoPolyLine
uid 2491,0
va (VaSet
vasetType 3
)
xt "27000,34000,36250,58000"
pts [
"36250,34000"
"27000,34000"
"27000,58000"
]
)
start &51
end &12
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2494,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2495,0
va (VaSet
font "Verdana,12,0"
)
xt "32250,32600,35350,34000"
st "TxD"
blo "32250,33800"
tm "WireNameMgr"
)
)
on &19
)
*64 (Wire
uid 2498,0
shape (OrthoPolyLine
uid 2499,0
va (VaSet
vasetType 3
)
xt "53750,46000,57000,58000"
pts [
"53750,46000"
"57000,46000"
"57000,58000"
]
)
start &49
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2502,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2503,0
va (VaSet
font "Verdana,12,0"
)
xt "55750,44600,62650,46000"
st "selSinCos"
blo "55750,45800"
tm "WireNameMgr"
)
)
on &20
)
*65 (Wire
uid 2506,0
optionalChildren [
*66 (BdJunction
uid 2911,0
ps "OnConnectorStrategy"
shape (Circle
uid 2912,0
va (VaSet
vasetType 1
)
xt "58600,43600,59400,44400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 2507,0
va (VaSet
vasetType 3
)
xt "53750,44000,59000,58000"
pts [
"53750,44000"
"59000,44000"
"59000,58000"
]
)
start &48
end &12
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2510,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2511,0
va (VaSet
font "Verdana,12,0"
)
xt "55750,42600,59350,44000"
st "outY"
blo "55750,43800"
tm "WireNameMgr"
)
)
on &21
)
*67 (Wire
uid 2514,0
shape (OrthoPolyLine
uid 2515,0
va (VaSet
vasetType 3
)
xt "53750,42000,61000,58000"
pts [
"53750,42000"
"61000,42000"
"61000,58000"
]
)
start &47
end &12
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2518,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2519,0
va (VaSet
font "Verdana,12,0"
)
xt "55750,40600,59450,42000"
st "outX"
blo "55750,41800"
tm "WireNameMgr"
)
)
on &22
)
*68 (Wire
uid 2552,0
shape (OrthoPolyLine
uid 2553,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "53750,36000,69000,36000"
pts [
"53750,36000"
"69000,36000"
]
)
start &54
end &23
sat 32
eat 1
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2558,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2559,0
va (VaSet
font "Verdana,12,0"
)
xt "55750,34600,59950,36000"
st "ioOut"
blo "55750,35800"
tm "WireNameMgr"
)
)
on &29
)
*69 (Wire
uid 2560,0
shape (OrthoPolyLine
uid 2561,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "53750,34000,69000,34000"
pts [
"53750,34000"
"69000,34000"
]
)
start &53
end &23
sat 32
eat 1
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2566,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2567,0
va (VaSet
font "Verdana,12,0"
)
xt "55750,32600,59250,34000"
st "ioEn"
blo "55750,33800"
tm "WireNameMgr"
)
)
on &30
)
*70 (Wire
uid 2568,0
shape (OrthoPolyLine
uid 2569,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "85000,34000,89000,58000"
pts [
"85000,34000"
"89000,34000"
"89000,58000"
]
)
start &23
end &12
sat 4
eat 4
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2574,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2575,0
va (VaSet
font "Verdana,12,0"
)
xt "87000,32600,88900,34000"
st "io"
blo "87000,33800"
tm "WireNameMgr"
)
)
on &27
)
*71 (Wire
uid 2576,0
shape (OrthoPolyLine
uid 2577,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "53750,38000,69000,38000"
pts [
"53750,38000"
"69000,38000"
]
)
start &55
end &23
sat 32
eat 2
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2582,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2583,0
va (VaSet
font "Verdana,12,0"
)
xt "55750,36600,58950,38000"
st "ioIn"
blo "55750,37800"
tm "WireNameMgr"
)
)
on &28
)
*72 (Wire
uid 2877,0
shape (OrthoPolyLine
uid 2878,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "61000,14000,68250,14000"
pts [
"68250,14000"
"61000,14000"
]
)
start &39
end &31
ss 0
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2881,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2882,0
va (VaSet
font "Verdana,12,0"
)
xt "63000,12600,71800,14000"
st "lowpassInY"
blo "63000,13800"
tm "WireNameMgr"
)
)
on &43
)
*73 (Wire
uid 2883,0
shape (OrthoPolyLine
uid 2884,0
va (VaSet
vasetType 3
)
xt "65000,18000,68250,18000"
pts [
"65000,18000"
"68250,18000"
]
)
end &36
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2887,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2888,0
va (VaSet
font "Verdana,12,0"
)
xt "65000,16600,68800,18000"
st "clock"
blo "65000,17800"
tm "WireNameMgr"
)
)
on &17
)
*74 (Wire
uid 2889,0
shape (OrthoPolyLine
uid 2890,0
va (VaSet
vasetType 3
)
xt "65000,20000,68250,20000"
pts [
"65000,20000"
"68250,20000"
]
)
end &38
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2893,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2894,0
va (VaSet
font "Verdana,12,0"
)
xt "65000,18600,69100,20000"
st "reset"
blo "65000,19800"
tm "WireNameMgr"
)
)
on &16
)
*75 (Wire
uid 2895,0
shape (OrthoPolyLine
uid 2896,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "85750,14000,93000,58000"
pts [
"85750,14000"
"93000,14000"
"93000,58000"
]
)
start &37
end &12
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2899,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2900,0
va (VaSet
font "Verdana,12,0"
)
xt "87750,12600,97550,14000"
st "lowpassOutY"
blo "87750,13800"
tm "WireNameMgr"
)
)
on &44
)
*76 (Wire
uid 2905,0
shape (OrthoPolyLine
uid 2906,0
va (VaSet
vasetType 3
)
xt "53000,16000,59000,44000"
pts [
"59000,44000"
"59000,20000"
"53000,20000"
"53000,16000"
]
)
start &66
end &31
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2909,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2910,0
va (VaSet
font "Verdana,12,0"
)
xt "54000,18600,57600,20000"
st "outY"
blo "54000,19800"
tm "WireNameMgr"
)
)
on &21
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *77 (PackageList
uid 142,0
stg "VerticalLayoutStrategy"
textVec [
*78 (Text
uid 143,0
va (VaSet
font "Verdana,8,1"
)
xt "0,0,6900,1000"
st "Package List"
blo "0,800"
)
*79 (MLText
uid 144,0
va (VaSet
)
xt "0,1000,17500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 145,0
stg "VerticalLayoutStrategy"
textVec [
*80 (Text
uid 146,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,0,30200,1000"
st "Compiler Directives"
blo "20000,800"
)
*81 (Text
uid 147,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,1000,32200,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*82 (MLText
uid 148,0
va (VaSet
isHidden 1
)
xt "20000,2000,32100,4400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*83 (Text
uid 149,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,4000,32800,5000"
st "Post-module directives:"
blo "20000,4800"
)
*84 (MLText
uid 150,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*85 (Text
uid 151,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,5000,32400,6000"
st "End-module directives:"
blo "20000,5800"
)
*86 (MLText
uid 152,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "-1604,-1604,141072,75916"
cachedDiagramExtent "0,0,109000,74000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
toPrinter 1
xMargin 48
yMargin 48
paperWidth 761
paperHeight 1077
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4"
unixPaperName "A4  (210mm x 297mm)"
windowsPaperName "A4"
windowsPaperType 9
scale 67
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 3478,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*87 (Text
va (VaSet
)
xt "1700,3200,6300,4400"
st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*88 (Text
va (VaSet
)
xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*89 (Text
va (VaSet
)
xt "1700,5600,2900,6800"
st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "1700,13200,1700,13200"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*90 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*91 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*92 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6000,1500,-6000,1500"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*93 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*94 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*95 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
st "I0"
blo "1250,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-5750,1500,-5750,1500"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*96 (Text
va (VaSet
)
xt "950,3500,3250,4500"
st "Library"
blo "950,4300"
)
*97 (Text
va (VaSet
)
xt "950,4500,7050,5500"
st "VhdlComponent"
blo "950,5300"
)
*98 (Text
va (VaSet
)
xt "950,5500,1550,6500"
st "I0"
blo "950,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6050,1500,-6050,1500"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-50,0,8050,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*99 (Text
va (VaSet
)
xt "450,3500,2750,4500"
st "Library"
blo "450,4300"
)
*100 (Text
va (VaSet
)
xt "450,4500,7550,5500"
st "VerilogComponent"
blo "450,5300"
)
*101 (Text
va (VaSet
)
xt "450,5500,1050,6500"
st "I0"
blo "450,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6550,1500,-6550,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*102 (Text
va (VaSet
)
xt "3400,4000,4600,5000"
st "eb1"
blo "3400,4800"
tm "HdlTextNameMgr"
)
*103 (Text
va (VaSet
)
xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1500,2200"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,5000,1200"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,9600,2200"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,18500,100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*104 (Text
va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*105 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,11000,100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*106 (Text
va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*107 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Verdana,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "0,7200,7000,8200"
st "Declarations"
blo "0,8000"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,8,1"
)
xt "0,8200,3400,9200"
st "Ports:"
blo "0,9000"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "0,9200,4800,10200"
st "Pre User:"
blo "0,10000"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,10200,22200,18200"
st "constant ioNb: positive := 8;
constant testOutBitNb: positive := 16;
constant patternAddressBitNb: positive := 9;

constant signalBitNb: positive := 16;
constant lowpassShiftBitNb: positive := 8;
constant clockFrequency : real := 60.0E6;
--constant clockFrequency : real := 66.0E6;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,8,1"
)
xt "0,18200,9000,19200"
st "Diagram Signals:"
blo "0,19000"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "0,7200,6000,8200"
st "Post User:"
blo "0,8000"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,7200,0,7200"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 31,0
usingSuid 1
emptyRow *108 (LEmptyRow
)
uid 1321,0
optionalChildren [
*109 (RefLabelRowHdr
)
*110 (TitleRowHdr
)
*111 (FilterRowHdr
)
*112 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*113 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*114 (GroupColHdr
tm "GroupColHdrMgr"
)
*115 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*116 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*117 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*118 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*119 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*120 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*121 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 12
suid 18,0
)
)
uid 2528,0
)
*122 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 3
suid 19,0
)
)
uid 2530,0
)
*123 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "RxD"
t "std_ulogic"
o 1
suid 20,0
)
)
uid 2532,0
)
*124 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "TxD"
t "std_ulogic"
o 2
suid 21,0
)
)
uid 2534,0
)
*125 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selSinCos"
t "std_ulogic"
o 13
suid 22,0
)
)
uid 2536,0
)
*126 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "outY"
t "std_ulogic"
o 11
suid 23,0
)
)
uid 2538,0
)
*127 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "outX"
t "std_ulogic"
o 10
suid 24,0
)
)
uid 2540,0
)
*128 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "io"
t "std_logic_vector"
b "(ioNb-1 DOWNTO 0)"
o 4
suid 26,0
)
)
uid 2592,0
)
*129 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 6
suid 27,0
)
)
uid 2594,0
)
*130 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ioOut"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 7
suid 28,0
)
)
uid 2596,0
)
*131 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ioEn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 5
suid 29,0
)
)
uid 2598,0
)
*132 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "lowpassInY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 8
suid 30,0
)
)
uid 2913,0
)
*133 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "lowpassOutY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 9
suid 31,0
)
)
uid 2915,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 1334,0
optionalChildren [
*134 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *135 (MRCItem
litem &108
pos 13
dimension 20
)
uid 1336,0
optionalChildren [
*136 (MRCItem
litem &109
pos 0
dimension 20
uid 1337,0
)
*137 (MRCItem
litem &110
pos 1
dimension 23
uid 1338,0
)
*138 (MRCItem
litem &111
pos 2
hidden 1
dimension 20
uid 1339,0
)
*139 (MRCItem
litem &121
pos 0
dimension 20
uid 2529,0
)
*140 (MRCItem
litem &122
pos 1
dimension 20
uid 2531,0
)
*141 (MRCItem
litem &123
pos 2
dimension 20
uid 2533,0
)
*142 (MRCItem
litem &124
pos 3
dimension 20
uid 2535,0
)
*143 (MRCItem
litem &125
pos 4
dimension 20
uid 2537,0
)
*144 (MRCItem
litem &126
pos 5
dimension 20
uid 2539,0
)
*145 (MRCItem
litem &127
pos 6
dimension 20
uid 2541,0
)
*146 (MRCItem
litem &128
pos 7
dimension 20
uid 2593,0
)
*147 (MRCItem
litem &129
pos 8
dimension 20
uid 2595,0
)
*148 (MRCItem
litem &130
pos 9
dimension 20
uid 2597,0
)
*149 (MRCItem
litem &131
pos 10
dimension 20
uid 2599,0
)
*150 (MRCItem
litem &132
pos 11
dimension 20
uid 2914,0
)
*151 (MRCItem
litem &133
pos 12
dimension 20
uid 2916,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 1340,0
optionalChildren [
*152 (MRCItem
litem &112
pos 0
dimension 20
uid 1341,0
)
*153 (MRCItem
litem &114
pos 1
dimension 50
uid 1342,0
)
*154 (MRCItem
litem &115
pos 2
dimension 100
uid 1343,0
)
*155 (MRCItem
litem &116
pos 3
dimension 50
uid 1344,0
)
*156 (MRCItem
litem &117
pos 4
dimension 100
uid 1345,0
)
*157 (MRCItem
litem &118
pos 5
dimension 100
uid 1346,0
)
*158 (MRCItem
litem &119
pos 6
dimension 50
uid 1347,0
)
*159 (MRCItem
litem &120
pos 7
dimension 80
uid 1348,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 1335,0
vaOverrides [
]
)
]
)
uid 1320,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *160 (LEmptyRow
)
uid 1350,0
optionalChildren [
*161 (RefLabelRowHdr
)
*162 (TitleRowHdr
)
*163 (FilterRowHdr
)
*164 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*165 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*166 (GroupColHdr
tm "GroupColHdrMgr"
)
*167 (NameColHdr
tm "GenericNameColHdrMgr"
)
*168 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*169 (InitColHdr
tm "GenericValueColHdrMgr"
)
*170 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*171 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 1362,0
optionalChildren [
*172 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *173 (MRCItem
litem &160
pos 0
dimension 20
)
uid 1364,0
optionalChildren [
*174 (MRCItem
litem &161
pos 0
dimension 20
uid 1365,0
)
*175 (MRCItem
litem &162
pos 1
dimension 23
uid 1366,0
)
*176 (MRCItem
litem &163
pos 2
hidden 1
dimension 20
uid 1367,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 1368,0
optionalChildren [
*177 (MRCItem
litem &164
pos 0
dimension 20
uid 1369,0
)
*178 (MRCItem
litem &166
pos 1
dimension 50
uid 1370,0
)
*179 (MRCItem
litem &167
pos 2
dimension 100
uid 1371,0
)
*180 (MRCItem
litem &168
pos 3
dimension 100
uid 1372,0
)
*181 (MRCItem
litem &169
pos 4
dimension 50
uid 1373,0
)
*182 (MRCItem
litem &170
pos 5
dimension 50
uid 1374,0
)
*183 (MRCItem
litem &171
pos 6
dimension 80
uid 1375,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 1363,0
vaOverrides [
]
)
]
)
uid 1349,0
type 1
)
activeModelName "BlockDiag"
)
