<?xml version="1.0" encoding="UTF-8"?>
<RadiantProject version="4.2" title="neorv32_upduino_v3" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
    <Options/>
    <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="lse" default_strategy="Strategy1">
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        <Source name="../../../rtl/core/neorv32_cpu_cp_fpu.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_cpu_cp_muldiv.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_cpu_cp_shifter.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_cpu_decompressor.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_cpu_regfile.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_debug_dm.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_debug_dtm.vhd" type="VHDL" type_short="VHDL">
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        </Source>
        <Source name="../../../rtl/core/neorv32_fifo.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_gpio.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_pwm.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_spi.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_uart.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_wdt.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_wishbone.vhd" type="VHDL" type_short="VHDL">
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        <Source name="../../../rtl/core/neorv32_xirq.vhd" type="VHDL" type_short="VHDL">
            <Options lib="neorv32"/>
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        <Source name="../../../rtl/core/neorv32_dmem.entity.vhd" type="VHDL" type_short="VHDL">
            <Options lib="neorv32"/>
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        <Source name="../../../rtl/core/neorv32_imem.entity.vhd" type="VHDL" type_short="VHDL">
            <Options lib="neorv32"/>
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        <Source name="neorv32_dmem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
            <Options lib="neorv32"/>
        </Source>
        <Source name="neorv32_imem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
            <Options lib="neorv32"/>
        </Source>
        <Source name="neorv32_upduino_v3_top.vhd" type="VHDL" type_short="VHDL">
            <Options lib="work" top_module="neorv32_upduino_v3_top"/>
        </Source>
        <Source name="system_pll/system_pll.ipx" type="IPX_Module" type_short="IPX">
            <Options/>
        </Source>
        <Source name="neorv32_upduino_v3.pdc" type="Physical Constraints File" type_short="PDC">
            <Options/>
        </Source>
        <Source name="source/impl_1.xcf" type="Programming Project File" type_short="Programming">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="neorv32_upduino_v3.sty"/>
</RadiantProject>
