-- VHDL Entity WaveformGenerator_test.waveformGen_tester.interface
--
-- Created:
--          by - remi.heredero.UNKNOWN (WE2330808)
--          at - 14:26:40 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

ENTITY waveformGen_tester IS
    GENERIC( 
        bitNb          : positive := 16;
        clockFrequency : real     := 60.0E6;
        phaseBitNb     : positive := 16;
        signalBitNb    : positive := 16
    );
    PORT( 
        polygon  : IN     unsigned (signalBitNb-1 DOWNTO 0);
        sawtooth : IN     unsigned (phaseBitNb-1 DOWNTO 0);
        sine     : IN     unsigned (signalBitNb-1 DOWNTO 0);
        square   : IN     unsigned (signalBitNb-1 DOWNTO 0);
        triangle : IN     unsigned (signalBitNb-1 DOWNTO 0);
        clock    : OUT    std_ulogic;
        en       : OUT    std_ulogic;
        reset    : OUT    std_ulogic;
        step     : OUT    unsigned (bitNb-1 DOWNTO 0)
    );

-- Declarations

END waveformGen_tester ;

