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st "g_dataWidth = c_dataWidth    ( positive )  "
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header ""
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iconMaskName "VhdlFileViewIcon.msk"
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
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st "dbg_leds"
blo "176000,14400"
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oxt "0,0,18000,5000"
text (MLText
uid 4481,0
va (VaSet
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st "


dbg_leds(7 downto 0) <= std_ulogic_vector(adr(9 downto 2)); -- no need to read LSBs since does +4 each time

dbg_leds(15 downto 8) <= std_ulogic_vector(instruction(7 downto 0));

dbg_leds(23 downto 16) <= std_ulogic_vector(ALUControl & \"000\" & resultSrc);

dbg_leds(31 downto 24) <= std_ulogic_vector(regwrite & immSrc & '0' & ALUSrcB & ALUSrcA);

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iconMaskName "TextFile.msk"
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tg (WTG
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stg "STSignalDisplayStrategy"
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va (VaSet
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xt "16625,88000,17375,88750"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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f (Text
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ro 270
va (VaSet
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xt "16600,78500,17800,88000"
st "in2 : std_uLogic"
blo "17600,88000"
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thePort (LogicalPort
decl (Decl
n "in2"
t "std_uLogic"
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ps "OnEdgeStrategy"
shape (Triangle
uid 4525,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
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xt "15625,84300,16375,85050"
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tg (CPTG
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ro 270
va (VaSet
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xt "15550,85000,16750,95200"
st "out1 : std_uLogic"
ju 2
blo "16550,85000"
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thePort (LogicalPort
m 1
decl (Decl
n "out1"
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shape (And
uid 4529,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "14000,85000,18000,88000"
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showPorts 0
oxt "31000,13000,38000,19000"
ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
textVec [
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uid 4531,0
va (VaSet
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font "Verdana,8,1"
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xt "15100,89200,18200,90200"
st "gates"
blo "15100,90000"
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va (VaSet
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font "Verdana,8,1"
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xt "15100,90200,18000,91200"
st "and2"
blo "15100,91000"
tm "CptNameMgr"
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uid 4533,0
va (VaSet
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font "Verdana,8,1"
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xt "15100,90200,19300,91200"
st "U_and1"
blo "15100,91000"
tm "InstanceNameMgr"
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text (MLText
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va (VaSet
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font "Verdana,8,0"
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xt "14500,93100,28600,94100"
st "delay = gateDelay    ( time )  "
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header ""
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elements [
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type "time"
value "gateDelay"
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viewicon (ZoomableIcon
uid 4537,0
sl 0
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fg "49152,49152,49152"
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iconMaskName "VhdlFileViewIcon.msk"
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portVis (PortSigDisplay
sN 0
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uid 4538,0
decl (Decl
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declText (MLText
uid 4539,0
va (VaSet
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xt "22000,28800,39000,29600"
st "SIGNAL out1        : std_uLogic"
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uid 4546,0
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shape (Triangle
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va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
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xt "55625,75000,56375,75750"
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tg (CPTG
uid 4558,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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ro 270
va (VaSet
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xt "49600,65500,50800,75000"
st "in1 : std_uLogic"
blo "50600,75000"
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thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
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uid 4560,0
ps "OnEdgeStrategy"
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isHidden 1
fg "0,65535,0"
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xt "53625,75000,54375,75750"
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tg (CPTG
uid 4562,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4563,0
ro 270
va (VaSet
isHidden 1
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xt "47600,65500,48800,75000"
st "in2 : std_uLogic"
blo "48600,75000"
)
)
thePort (LogicalPort
decl (Decl
n "in2"
t "std_uLogic"
o 2
)
)
)
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uid 4564,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4565,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
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xt "54625,71300,55375,72050"
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tg (CPTG
uid 4566,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4567,0
ro 270
va (VaSet
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xt "48550,72000,49750,82200"
st "out1 : std_uLogic"
ju 2
blo "49550,72000"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 3
)
)
)
]
shape (And
uid 4547,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "53000,72000,57000,75000"
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showPorts 0
oxt "31000,13000,38000,19000"
ttg (MlTextGroup
uid 4548,0
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stg "VerticalLayoutStrategy"
textVec [
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uid 4549,0
va (VaSet
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font "Verdana,8,1"
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xt "54100,76200,57200,77200"
st "gates"
blo "54100,77000"
tm "BdLibraryNameMgr"
)
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uid 4550,0
va (VaSet
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font "Verdana,8,1"
)
xt "54100,77200,57000,78200"
st "and2"
blo "54100,78000"
tm "CptNameMgr"
)
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uid 4551,0
va (VaSet
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font "Verdana,8,1"
)
xt "54100,77200,58300,78200"
st "U_and2"
blo "54100,78000"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4552,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4553,0
text (MLText
uid 4554,0
va (VaSet
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font "Verdana,8,0"
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xt "53500,80100,67600,81100"
st "delay = gateDelay    ( time )  "
)
header ""
)
elements [
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name "delay"
type "time"
value "gateDelay"
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)
viewicon (ZoomableIcon
uid 4555,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
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xt "53250,73250,54750,74750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
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viewiconposition 0
portVis (PortSigDisplay
sN 0
sT 1
)
archFileType "UNKNOWN"
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uid 4586,0
decl (Decl
n "en1"
t "std_uLogic"
o 21
suid 100,0
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declText (MLText
uid 4587,0
va (VaSet
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xt "22000,22400,39000,23200"
st "SIGNAL en1         : std_uLogic"
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uid 5835,0
lang 11
decl (Decl
n "btns"
t "std_ulogic_vector"
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o 1
suid 101,0
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declText (MLText
uid 5836,0
va (VaSet
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xt "22000,2400,50000,3200"
st "btns        : std_ulogic_vector(g_btnsNb-1 DOWNTO 0)"
)
)
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shape (CompositeShape
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va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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uid 5843,0
sl 0
ro 180
xt "72625,109500,73375,111000"
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ro 180
xt "73000,109000,73000,109500"
pts [
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)
stc 0
sf 1
tg (WTG
uid 5845,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5846,0
ro 90
va (VaSet
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xt "72400,112000,73600,114900"
st "btns"
blo "72600,112000"
tm "WireNameMgr"
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)
)
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uid 5847,0
lang 11
decl (Decl
n "leds"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 6
suid 102,0
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declText (MLText
uid 5848,0
va (VaSet
font "Courier New,8,0"
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xt "22000,6400,51500,7200"
st "leds        : std_ulogic_vector(g_dataWidth-1 DOWNTO 0)"
)
)
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shape (CompositeShape
uid 5854,0
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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uid 5855,0
sl 0
xt "74625,109500,75375,111000"
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(Line
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sl 0
xt "75000,109000,75000,109500"
pts [
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stc 0
sf 1
tg (WTG
uid 5857,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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ro 90
va (VaSet
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xt "74400,112000,75600,114800"
st "leds"
blo "74600,112000"
tm "WireNameMgr"
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)
)
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uid 6827,0
optionalChildren [
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uid 6799,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6800,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "36250,79625,37000,80375"
)
tg (CPTG
uid 6801,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
font "Verdana,8,0"
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xt "38000,79500,41600,80500"
st "address"
blo "38000,80300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "address"
t "unsigned"
b "(g_dataWidth-1 DOWNTO 0)"
o 1
suid 27,0
)
)
)
*120 (CptPort
uid 6803,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6804,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "38625,77250,39375,78000"
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tg (CPTG
uid 6805,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
font "Verdana,8,0"
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xt "38480,78000,40080,79000"
st "clk"
blo "38480,78800"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "clk"
t "std_ulogic"
o 2
suid 28,0
)
)
)
*121 (CptPort
uid 6807,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6808,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51000,80625,51750,81375"
)
tg (CPTG
uid 6809,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6810,0
va (VaSet
font "Verdana,8,0"
)
xt "45800,80500,50000,81500"
st "readData"
ju 2
blo "50000,81300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "readData"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 6
suid 29,0
)
)
)
*122 (CptPort
uid 6811,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6812,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,81625,37000,82375"
)
tg (CPTG
uid 6813,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6814,0
va (VaSet
font "Verdana,8,0"
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xt "38000,81500,42400,82500"
st "writeData"
blo "38000,82300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "writeData"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 4
suid 31,0
)
)
)
*123 (CptPort
uid 6815,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6816,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43625,77250,44375,78000"
)
tg (CPTG
uid 6817,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6818,0
ro 270
va (VaSet
font "Verdana,8,0"
)
xt "43500,78000,44500,83700"
st "writeEnable"
ju 2
blo "44300,78000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "writeEnable"
t "std_ulogic"
o 5
suid 32,0
)
)
)
*124 (CptPort
uid 6819,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6820,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45625,77250,46375,78000"
)
tg (CPTG
uid 6821,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6822,0
ro 270
va (VaSet
font "Verdana,8,0"
)
xt "45500,79000,46500,80500"
st "en"
ju 2
blo "46300,79000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 38,0
)
)
)
*125 (CommentGraphic
uid 6823,0
shape (PolyLine2D
pts [
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]
uid 6824,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "38000,78000,39000,80000"
)
oxt "20000,15000,21000,17000"
)
*126 (CommentGraphic
uid 6825,0
shape (PolyLine2D
pts [
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]
uid 6826,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "39000,78000,40000,80000"
)
oxt "21000,15000,22000,17000"
)
]
shape (Rectangle
uid 6828,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "37000,78000,51000,85000"
fos 1
)
oxt "19000,15000,33000,22000"
ttg (MlTextGroup
uid 6829,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 6830,0
va (VaSet
font "Verdana,9,1"
)
xt "36750,85800,44350,87000"
st "HEIRV32_MC"
blo "36750,86800"
tm "BdLibraryNameMgr"
)
*128 (Text
uid 6831,0
va (VaSet
font "Verdana,9,1"
)
xt "36750,87000,50250,88200"
st "instructionDataMemory"
blo "36750,88000"
tm "CptNameMgr"
)
*129 (Text
uid 6832,0
va (VaSet
font "Verdana,9,1"
)
xt "36750,88200,47850,89400"
st "U_instrDataMemory"
blo "36750,89200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 6833,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 6834,0
text (MLText
uid 6835,0
va (VaSet
font "Courier New,8,0"
)
xt "32000,90600,58500,93000"
st "g_dataWidth   = c_dataWidth        ( positive )  
g_addrWidth   = c_bramAddrWidth    ( positive )  
g_programFile = g_programFile      ( string   )  "
)
header ""
)
elements [
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name "g_dataWidth"
type "positive"
value "c_dataWidth"
)
(GiElement
name "g_addrWidth"
type "positive"
value "c_bramAddrWidth"
)
(GiElement
name "g_programFile"
type "string"
value "g_programFile"
)
]
)
viewicon (ZoomableIcon
uid 6836,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "37250,83250,38750,84750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
sed 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*130 (SaComponent
uid 6849,0
optionalChildren [
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uid 6837,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6838,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,84625,65750,85375"
)
tg (CPTG
uid 6839,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6840,0
va (VaSet
font "Verdana,8,0"
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xt "58900,84500,64000,85500"
st "instruction"
ju 2
blo "64000,85300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "instruction"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 3
suid 1,0
)
)
)
*132 (CptPort
uid 6841,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6842,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60625,79250,61375,80000"
)
tg (CPTG
uid 6843,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6844,0
ro 270
va (VaSet
font "Verdana,8,0"
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xt "60500,81000,61500,84100"
st "irWrite"
ju 2
blo "61300,81000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "irWrite"
t "std_ulogic"
o 1
suid 2,0
)
)
)
*133 (CptPort
uid 6845,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6846,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "54250,80625,55000,81375"
)
tg (CPTG
uid 6847,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6848,0
va (VaSet
font "Verdana,8,0"
)
xt "56000,80500,60200,81500"
st "readData"
blo "56000,81300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "readData"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 2
suid 3,0
)
)
)
]
shape (Rectangle
uid 6850,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "55000,80000,65000,86000"
)
oxt "27000,15000,37000,21000"
ttg (MlTextGroup
uid 6851,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 6852,0
va (VaSet
font "Verdana,9,1"
)
xt "54850,86800,62450,88000"
st "HEIRV32_MC"
blo "54850,87800"
tm "BdLibraryNameMgr"
)
*135 (Text
uid 6853,0
va (VaSet
font "Verdana,9,1"
)
xt "54850,88000,67150,89200"
st "instructionForwarder"
blo "54850,89000"
tm "CptNameMgr"
)
*136 (Text
uid 6854,0
va (VaSet
font "Verdana,9,1"
)
xt "54850,89200,63750,90400"
st "U_instrForward"
blo "54850,90200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 6855,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 6856,0
text (MLText
uid 6857,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "55000,91600,78500,92400"
st "g_dataWidth = c_dataWidth    ( positive )  "
)
header ""
)
elements [
(GiElement
name "g_dataWidth"
type "positive"
value "c_dataWidth"
)
]
)
viewicon (ZoomableIcon
uid 6858,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "55250,84250,56750,85750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*137 (SaComponent
uid 6931,0
optionalChildren [
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uid 6859,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6860,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "98000,45625,98750,46375"
)
tg (CPTG
uid 6861,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6862,0
va (VaSet
font "Verdana,12,0"
)
xt "88400,45300,97000,46700"
st "ALUControl"
ju 2
blo "97000,46500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "ALUControl"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 8
suid 2,0
)
)
)
*139 (CptPort
uid 6863,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6864,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "98000,49625,98750,50375"
)
tg (CPTG
uid 6865,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6866,0
va (VaSet
font "Verdana,12,0"
)
xt "91100,49300,97000,50700"
st "ALUSrcA"
ju 2
blo "97000,50500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "ALUSrcA"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 9
suid 3,0
)
)
)
*140 (CptPort
uid 6867,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6868,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "98000,47625,98750,48375"
)
tg (CPTG
uid 6869,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6870,0
va (VaSet
font "Verdana,12,0"
)
xt "91100,47300,97000,48700"
st "ALUSrcB"
ju 2
blo "97000,48500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "ALUSrcB"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 10
suid 4,0
)
)
)
*141 (CptPort
uid 6871,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6872,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "98000,51625,98750,52375"
)
tg (CPTG
uid 6873,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6874,0
va (VaSet
font "Verdana,12,0"
)
xt "91800,51300,97000,52700"
st "immSrc"
ju 2
blo "97000,52500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "immSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 14
suid 5,0
)
)
)
*142 (CptPort
uid 6875,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6876,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,51625,81000,52375"
)
tg (CPTG
uid 6877,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6878,0
va (VaSet
font "Verdana,12,0"
)
xt "82000,51300,84400,52700"
st "op"
blo "82000,52500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "op"
t "std_ulogic_vector"
b "(6 DOWNTO 0)"
o 5
suid 6,0
)
)
)
*143 (CptPort
uid 6879,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6880,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,48625,81000,49375"
)
tg (CPTG
uid 6881,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6882,0
va (VaSet
font "Verdana,12,0"
)
xt "82000,48300,87500,49700"
st "IRWrite"
blo "82000,49500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "IRWrite"
t "std_ulogic"
o 11
suid 7,0
)
)
)
*144 (CptPort
uid 6883,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6884,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,46625,81000,47375"
)
tg (CPTG
uid 6885,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6886,0
va (VaSet
font "Verdana,12,0"
)
xt "82000,46300,89200,47700"
st "memWrite"
blo "82000,47500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "memWrite"
t "std_ulogic"
o 15
suid 8,0
)
)
)
*145 (CptPort
uid 6887,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6888,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,42625,81000,43375"
)
tg (CPTG
uid 6889,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8096,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8097,0
text (MLText
uid 8098,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "136000,93600,159500,95200"
st "g_datawidth = c_dataWidth    ( positive )  
g_tALU      = 120 ps         ( time     )  "
)
header ""
)
elements [
(GiElement
name "g_datawidth"
type "positive"
value "c_dataWidth"
)
(GiElement
name "g_tALU"
type "time"
value "120 ps"
)
]
)
viewicon (ZoomableIcon
uid 8099,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "136250,88250,137750,89750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*219 (SaComponent
uid 8152,0
optionalChildren [
*220 (CptPort
uid 8100,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8101,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92625,70250,93375,71000"
)
tg (CPTG
uid 8102,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8103,0
va (VaSet
font "Verdana,12,0"
)
xt "91424,71345,93824,72745"
st "clk"
ju 2
blo "93824,72545"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "clk"
t "std_ulogic"
o 5
suid 1,0
)
)
)
*221 (CptPort
uid 8104,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8105,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "89250,75625,90000,76375"
)
tg (CPTG
uid 8106,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8107,0
va (VaSet
font "Verdana,12,0"
)
xt "91000,75300,95500,76700"
st "addr1"
blo "91000,76500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "addr1"
t "std_ulogic_vector"
b "(4 DOWNTO 0)"
o 1
suid 2,0
)
)
)
*222 (CptPort
uid 8108,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8109,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "89250,82625,90000,83375"
)
tg (CPTG
uid 8110,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8111,0
va (VaSet
font "Verdana,12,0"
)
xt "91000,82300,98000,83700"
st "writeData"
blo "91000,83500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "writeData"
t "std_ulogic_vector"
b "(g_dataWidth - 1 DOWNTO 0)"
o 4
suid 3,0
)
)
)
*223 (CptPort
uid 8112,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8113,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "107000,75625,107750,76375"
)
tg (CPTG
uid 8114,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8115,0
va (VaSet
font "Verdana,12,0"
)
xt "102700,75300,106000,76700"
st "RD1"
ju 2
blo "106000,76500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "RD1"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 8
suid 4,0
)
)
)
*224 (CptPort
uid 8116,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8117,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "107000,79625,107750,80375"
)
tg (CPTG
uid 8118,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8119,0
va (VaSet
font "Verdana,12,0"
)
xt "102700,79300,106000,80700"
st "RD2"
ju 2
blo "106000,80500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "RD2"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 9
suid 5,0
)
)
)
*225 (CptPort
uid 8120,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8121,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "99625,70250,100375,71000"
)
tg (CPTG
uid 8122,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8123,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "99300,72000,100700,81900"
st "writeEnable3"
ju 2
blo "100500,72000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "writeEnable3"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*226 (CptPort
uid 8124,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8125,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "95625,70250,96375,71000"
)
tg (CPTG
uid 8126,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8127,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "95300,72000,96700,74500"
st "rst"
ju 2
blo "96500,72000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "rst"
t "std_ulogic"
o 7
suid 7,0
)
)
)
*227 (CptPort
uid 8128,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8129,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "89250,77625,90000,78375"
)
tg (CPTG
uid 8130,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8131,0
va (VaSet
font "Verdana,12,0"
)
xt "91000,77300,95500,78700"
st "addr2"
blo "91000,78500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "addr2"
t "std_ulogic_vector"
b "(4 DOWNTO 0)"
o 2
suid 8,0
)
)
)
*228 (CptPort
uid 8132,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8133,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "89250,79625,90000,80375"
)
tg (CPTG
uid 8134,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8135,0
va (VaSet
font "Verdana,12,0"
)
xt "91000,79300,95500,80700"
st "addr3"
blo "91000,80500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "addr3"
t "std_ulogic_vector"
b "(4 DOWNTO 0)"
o 3
suid 9,0
)
)
)
*229 (CptPort
uid 8136,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8137,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102625,70250,103375,71000"
)
tg (CPTG
uid 8138,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8139,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "102300,72000,103700,74400"
st "en"
ju 2
blo "103500,72000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 10
suid 10,0
)
)
)
*230 (CptPort
uid 8140,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8141,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101625,85000,102375,85750"
)
tg (CPTG
uid 8142,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8143,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "101300,80400,102700,84000"
st "btns"
blo "102500,84000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "btns"
t "std_ulogic_vector"
b "(g_btnsNb-1 DOWNTO 0)"
o 11
suid 11,0
)
)
)
*231 (CptPort
uid 8144,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8145,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103625,85000,104375,85750"
)
tg (CPTG
uid 8146,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8147,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "103300,80600,104700,84000"
st "leds"
blo "104500,84000"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "leds"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 12
suid 12,0
)
)
)
*232 (CommentGraphic
uid 8148,0
shape (PolyLine2D
pts [
"91000,71000"
"93000,74000"
]
uid 8149,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "91000,71000,93000,74000"
)
oxt "17000,21000,19000,24000"
)
*233 (CommentGraphic
uid 8150,0
shape (PolyLine2D
pts [
"93000,74000"
"95000,71000"
]
uid 8151,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "93000,71000,95000,74000"
)
oxt "19000,21000,21000,24000"
)
]
shape (Rectangle
uid 8153,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "90000,71000,107000,85000"
fos 1
)
oxt "16000,21000,33000,35000"
ttg (MlTextGroup
uid 8154,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*234 (Text
uid 8155,0
va (VaSet
font "Verdana,9,1"
)
xt "80050,69300,85050,70500"
st "HEIRV32"
blo "80050,70300"
tm "BdLibraryNameMgr"
)
*235 (Text
uid 8156,0
va (VaSet
font "Verdana,9,1"
)
xt "80050,70500,86950,71700"
st "registerFile"
blo "80050,71500"
tm "CptNameMgr"
)
*236 (Text
uid 8157,0
va (VaSet
font "Verdana,9,1"
)
xt "80050,71700,88250,72900"
st "U_registerFile"
blo "80050,72700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8158,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8159,0
text (MLText
uid 8160,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "91000,88600,114500,92600"
st "g_dataWidth = c_dataWidth    ( positive )  
g_btnsNb    = g_btnsNb       ( positive )  
g_tRfRd     = 100 ps         ( time     )  
g_tRfWr     = 60 ps          ( time     )  
g_tSetup    = 50 ps          ( time     )  "
)
header ""
)
elements [
(GiElement
name "g_dataWidth"
type "positive"
value "c_dataWidth"
)
(GiElement
name "g_btnsNb"
type "positive"
value "g_btnsNb"
)
(GiElement
name "g_tRfRd"
type "time"
value "100 ps"
)
(GiElement
name "g_tRfWr"
type "time"
value "60 ps"
)
(GiElement
name "g_tSetup"
type "time"
value "50 ps"
)
]
)
viewicon (ZoomableIcon
uid 8161,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "90250,83250,91750,84750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
sed 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*237 (Wire
uid 342,0
shape (OrthoPolyLine
uid 343,0
va (VaSet
vasetType 3
)
xt "11000,38000,14000,38000"
pts [
"11000,38000"
"14000,38000"
]
)
start &12
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 348,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 349,0
va (VaSet
isHidden 1
)
xt "13000,36800,15200,38000"
st "clk"
blo "13000,37800"
tm "WireNameMgr"
)
)
on &16
)
*238 (Wire
uid 350,0
shape (OrthoPolyLine
uid 351,0
va (VaSet
vasetType 3
)
xt "11000,40000,14000,40000"
pts [
"11000,40000"
"14000,40000"
]
)
start &13
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 356,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 357,0
va (VaSet
isHidden 1
)
xt "13000,38800,15100,40000"
st "rst"
blo "13000,39800"
tm "WireNameMgr"
)
)
on &15
)
*239 (Wire
uid 396,0
shape (OrthoPolyLine
uid 397,0
va (VaSet
vasetType 3
)
xt "16000,74000,16000,75250"
pts [
"16000,74000"
"16000,75250"
]
)
end &161
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 402,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 403,0
va (VaSet
)
xt "15059,72035,17259,73235"
st "clk"
blo "15059,73035"
tm "WireNameMgr"
)
)
on &16
)
*240 (Wire
uid 426,0
shape (OrthoPolyLine
uid 427,0
va (VaSet
vasetType 3
)
xt "10000,81000,13250,81000"
pts [
"10000,81000"
"13250,81000"
]
)
end &165
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 432,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 433,0
va (VaSet
)
xt "11000,79800,13100,81000"
st "rst"
blo "11000,80800"
tm "WireNameMgr"
)
)
on &15
)
*241 (Wire
uid 716,0
shape (OrthoPolyLine
uid 717,0
va (VaSet
vasetType 3
)
xt "17000,43000,80250,90000"
pts [
"17000,88000"
"17000,90000"
"20000,90000"
"20000,43000"
"80250,43000"
]
)
start &100
end &145
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 720,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 721,0
va (VaSet
)
xt "17000,89800,21800,91000"
st "PCWrite"
blo "17000,90800"
tm "WireNameMgr"
)
)
on &17
)
*242 (Wire
uid 782,0
optionalChildren [
*243 (BdJunction
uid 4060,0
ps "OnConnectorStrategy"
shape (Circle
uid 4061,0
va (VaSet
vasetType 1
)
xt "21600,78600,22400,79400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 783,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "18750,79000,26000,79000"
pts [
"18750,79000"
"26000,79000"
]
)
start &162
end &20
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 786,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 787,0
va (VaSet
)
xt "24000,77800,26200,79000"
st "PC"
blo "24000,78800"
tm "WireNameMgr"
)
)
on &14
)
*244 (Wire
uid 790,0
optionalChildren [
*245 (BdJunction
uid 804,0
ps "OnConnectorStrategy"
shape (Circle
uid 805,0
va (VaSet
vasetType 1
)
xt "21600,100600,22400,101400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 791,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "8000,79000,28000,101000"
pts [
"13250,79000"
"8000,79000"
"8000,101000"
"28000,101000"
]
)
start &163
end &53
es 0
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 794,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 795,0
va (VaSet
)
xt "9000,77800,13600,79000"
st "PCNext"
blo "9000,78800"
tm "WireNameMgr"
)
)
on &18
)
*246 (Wire
uid 798,0
shape (OrthoPolyLine
uid 799,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "22000,81000,26000,101000"
pts [
"22000,101000"
"22000,81000"
"26000,81000"
]
)
start &245
end &23
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 802,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 803,0
va (VaSet
)
xt "22000,79800,26600,81000"
st "PCNext"
blo "22000,80800"
tm "WireNameMgr"
)
)
on &18
)
*247 (Wire
uid 838,0
shape (OrthoPolyLine
uid 839,0
va (VaSet
vasetType 3
)
xt "29000,45000,80250,78500"
pts [
"29000,78500"
"29000,45000"
"80250,45000"
]
)
start &22
end &153
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 842,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 843,0
ro 270
va (VaSet
)
xt "27800,73000,29000,77000"
st "adrSrc"
blo "28800,77000"
tm "WireNameMgr"
)
s (Text
uid 2894,0
ro 270
va (VaSet
)
xt "29000,77000,29000,77000"
blo "29100,77100"
tm "SignalTypeMgr"
)
)
on &60
)
*248 (Wire
uid 852,0
shape (OrthoPolyLine
uid 853,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "30000,80000,36250,80000"
pts [
"30000,80000"
"36250,80000"
]
)
start &21
end &119
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 856,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 857,0
va (VaSet
)
xt "33000,78800,35300,80000"
st "adr"
blo "33000,79800"
tm "WireNameMgr"
)
s (Text
uid 2895,0
va (VaSet
)
xt "33000,80000,33000,80000"
blo "33000,80000"
tm "SignalTypeMgr"
)
)
on &27
)
*249 (Wire
uid 872,0
shape (OrthoPolyLine
uid 873,0
va (VaSet
vasetType 3
)
xt "39000,75000,39000,77250"
pts [
"39000,75000"
"39000,77250"
]
)
end &120
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 878,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 879,0
va (VaSet
)
xt "38000,72800,40200,74000"
st "clk"
blo "38000,73800"
tm "WireNameMgr"
)
)
on &16
)
*250 (Wire
uid 880,0
optionalChildren [
*251 (BdJunction
uid 3596,0
ps "OnConnectorStrategy"
shape (Circle
uid 3597,0
va (VaSet
vasetType 1
)
xt "52600,80600,53400,81400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 881,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "51750,81000,175250,99000"
pts [
"51750,81000"
"53000,81000"
"53000,99000"
"168000,99000"
"168000,86000"
"175250,86000"
]
)
start &121
end &194
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 886,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 887,0
va (VaSet
)
xt "172000,84800,174900,86000"
st "data"
blo "172000,85800"
tm "WireNameMgr"
)
)
on &31
)
*252 (Wire
uid 898,0
optionalChildren [
*253 (BdJunction
uid 2430,0
ps "OnConnectorStrategy"
shape (Circle
uid 2431,0
va (VaSet
vasetType 1
)
xt "111600,86600,112400,87400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 899,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "31000,80000,112000,97000"
pts [
"107750,80000"
"112000,80000"
"112000,97000"
"31000,97000"
"31000,82000"
"36250,82000"
]
)
start &224
end &122
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 904,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 905,0
va (VaSet
)
xt "31000,80800,36500,82000"
st "writeData"
blo "31000,81800"
tm "WireNameMgr"
)
)
on &28
)
*254 (Wire
uid 1106,0
shape (OrthoPolyLine
uid 1107,0
va (VaSet
vasetType 3
)
xt "44000,47000,80250,77250"
pts [
"44000,77250"
"44000,47000"
"80250,47000"
]
)
start &123
end &144
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 1110,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1111,0
ro 270
va (VaSet
)
xt "42800,70300,44000,76000"
st "memWrite"
blo "43800,76000"
tm "WireNameMgr"
)
)
on &29
)
*255 (Wire
uid 1164,0
optionalChildren [
*256 (BdJunction
uid 4578,0
ps "OnConnectorStrategy"
shape (Circle
uid 4579,0
va (VaSet
vasetType 1
)
xt "53600,76600,54400,77400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1165,0
va (VaSet
vasetType 3
)
xt "47000,49000,80250,79250"
pts [
"61000,79250"
"61000,77000"
"47000,77000"
"47000,49000"
"80250,49000"
]
)
start &132
end &143
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 1168,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1169,0
ro 270
va (VaSet
isHidden 1
)
xt "59800,73250,61000,77750"
st "IRWrite"
blo "60800,77750"
tm "WireNameMgr"
)
)
on &30
)
*257 (Wire
uid 1274,0
optionalChildren [
*258 (BdJunction
uid 2374,0
ps "OnConnectorStrategy"
shape (Circle
uid 2375,0
va (VaSet
vasetType 1
)
xt "48600,65600,49400,66400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1275,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40000,66000,52250,66000"
pts [
"40000,66000"
"52250,66000"
]
)
start &74
end &83
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1276,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1277,0
va (VaSet
)
xt "50000,64800,52800,66000"
st "PCu"
blo "50000,65800"
tm "WireNameMgr"
)
)
on &78
)
*259 (Wire
uid 1286,0
shape (OrthoPolyLine
uid 1287,0
va (VaSet
vasetType 3
)
xt "49000,68000,52250,68000"
pts [
"49000,68000"
"52250,68000"
]
)
end &80
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1292,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1293,0
va (VaSet
)
xt "50000,66800,52100,68000"
st "rst"
blo "50000,67800"
tm "WireNameMgr"
)
)
on &15
)
*260 (Wire
uid 1294,0
shape (OrthoPolyLine
uid 1295,0
va (VaSet
vasetType 3
)
xt "55000,61000,55000,62250"
pts [
"55000,61000"
"55000,62250"
]
)
end &82
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1300,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1301,0
va (VaSet
)
xt "54059,59035,56259,60235"
st "clk"
blo "54059,60035"
tm "WireNameMgr"
)
)
on &16
)
*261 (Wire
uid 1304,0
shape (OrthoPolyLine
uid 1305,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "57750,66000,120250,74000"
pts [
"57750,66000"
"112000,66000"
"112000,74000"
"120250,74000"
]
)
start &84
end &184
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 1308,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1309,0
va (VaSet
)
xt "115000,72800,118700,74000"
st "oldPC"
blo "115000,73800"
tm "WireNameMgr"
)
)
on &32
)
*262 (Wire
uid 1314,0
optionalChildren [
*263 (Ripper
uid 1328,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"66999,51050"
"67999,52050"
]
uid 1329,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66999,51050,67999,52050"
)
)
*264 (Ripper
uid 1339,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"66999,53000"
"67999,54000"
]
uid 1340,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66999,53000,67999,54000"
)
)
*265 (Ripper
uid 1350,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"66999,55000"
"67999,56000"
]
uid 1351,0
va (VaSet
vasetType 3
)
xt "66999,55000,67999,56000"
)
)
*266 (BdJunction
uid 1800,0
ps "OnConnectorStrategy"
shape (Circle
uid 1801,0
va (VaSet
vasetType 1
)
xt "66600,84600,67400,85400"
radius 400
)
)
*267 (Ripper
uid 1816,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"66999,77000"
"67999,78000"
]
uid 1817,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66999,77000,67999,78000"
)
)
*268 (Ripper
uid 1824,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"66999,79000"
"67999,80000"
]
uid 1825,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66999,79000,67999,80000"
)
)
*269 (Ripper
uid 1834,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"66999,75000"
"67999,76000"
]
uid 1835,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66999,75000,67999,76000"
)
)
]
shape (OrthoPolyLine
uid 1315,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "65750,50000,67000,85000"
pts [
"65750,85000"
"67000,85000"
"67000,50000"
]
)
start &131
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1318,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1319,0
va (VaSet
isHidden 1
)
xt "67000,83800,73800,85000"
st "instruction"
blo "67000,84800"
tm "WireNameMgr"
)
)
on &40
)
*270 (Wire
uid 1322,0
shape (OrthoPolyLine
uid 1323,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68005,52000,80250,52050"
pts [
"68005,52050"
"74000,52050"
"74000,52000"
"80250,52000"
]
)
start &263
end &142
sat 32
eat 32
sty 1
sl "(6 DOWNTO 0)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1327,0
va (VaSet
)
xt "71000,50800,80400,52000"
st "instruction(6:0)"
blo "71000,51800"
tm "WireNameMgr"
)
)
on &40
)
*271 (Wire
uid 1333,0
shape (OrthoPolyLine
uid 1334,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68005,54000,80250,54000"
pts [
"68005,54000"
"80250,54000"
]
)
start &264
end &149
sat 32
eat 32
sty 1
sl "(14 DOWNTO 12)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1337,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1338,0
va (VaSet
)
xt "71000,52800,81800,54000"
st "instruction(14:12)"
blo "71000,53800"
tm "WireNameMgr"
)
)
on &40
)
*272 (Wire
uid 1344,0
shape (OrthoPolyLine
uid 1345,0
va (VaSet
vasetType 3
)
xt "68005,56000,80250,56000"
pts [
"68005,56000"
"80250,56000"
]
)
start &265
end &150
sat 32
eat 32
sl "(30)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1348,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1349,0
va (VaSet
)
xt "71000,54800,80000,56000"
st "instruction(30)"
blo "71000,55800"
tm "WireNameMgr"
)
)
on &40
)
*273 (Wire
uid 1354,0
shape (OrthoPolyLine
uid 1355,0
va (VaSet
vasetType 3
)
xt "89000,59750,147000,82000"
pts [
"145750,82000"
"147000,82000"
"147000,61000"
"89000,61000"
"89000,59750"
]
)
start &215
end &148
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1360,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1361,0
ro 270
va (VaSet
)
xt "145800,78200,147000,81000"
st "zero"
blo "146800,81000"
tm "WireNameMgr"
)
)
on &33
)
*274 (Wire
uid 1368,0
shape (OrthoPolyLine
uid 1369,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "98750,44000,179000,83749"
pts [
"98750,44000"
"179000,44000"
"179000,83749"
]
)
start &147
end &192
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1374,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1375,0
ro 270
va (VaSet
)
xt "177800,75700,179000,81000"
st "resultSrc"
blo "178800,81000"
tm "WireNameMgr"
)
)
on &34
)
*275 (Wire
uid 1380,0
shape (OrthoPolyLine
uid 1381,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "98750,46000,141000,77027"
pts [
"98750,46000"
"141000,46000"
"141000,77027"
]
)
start &138
end &211
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1386,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1387,0
ro 270
va (VaSet
)
xt "139800,67700,141000,75000"
st "ALUControl"
blo "140800,75000"
tm "WireNameMgr"
)
)
on &35
)
*276 (Wire
uid 1392,0
shape (OrthoPolyLine
uid 1393,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "98750,48000,128000,86749"
pts [
"98750,48000"
"128000,48000"
"128000,86749"
]
)
start &140
end &172
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1398,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1399,0
ro 270
va (VaSet
)
xt "126800,79700,128000,85000"
st "ALUSrcB"
blo "127800,85000"
tm "WireNameMgr"
)
)
on &36
)
*277 (Wire
uid 1402,0
shape (OrthoPolyLine
uid 1403,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "98750,50000,124000,71749"
pts [
"98750,50000"
"124000,50000"
"124000,71749"
]
)
start &139
end &182
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1408,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1409,0
ro 270
va (VaSet
)
xt "122800,63600,124000,69000"
st "ALUSrcA"
blo "123800,69000"
tm "WireNameMgr"
)
)
on &37
)
*278 (Wire
uid 1412,0
shape (OrthoPolyLine
uid 1413,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "98750,52000,108000,90000"
pts [
"98750,52000"
"108000,52000"
"108000,90000"
"105750,90000"
]
)
start &141
end &204
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1418,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1419,0
va (VaSet
)
xt "100750,50800,105250,52000"
st "immSrc"
blo "100750,51800"
tm "WireNameMgr"
)
)
on &38
)
*279 (Wire
uid 1666,0
shape (OrthoPolyLine
uid 1667,0
va (VaSet
vasetType 3
)
xt "85000,36000,85000,37250"
pts [
"85000,36000"
"85000,37250"
]
)
end &151
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1672,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1673,0
va (VaSet
)
xt "84059,34035,86259,35235"
st "clk"
blo "84059,35035"
tm "WireNameMgr"
)
)
on &16
)
*280 (Wire
uid 1674,0
shape (OrthoPolyLine
uid 1675,0
va (VaSet
vasetType 3
)
xt "89000,36000,89000,37250"
pts [
"89000,36000"
"89000,37250"
]
)
end &152
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1680,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1681,0
va (VaSet
)
xt "88000,33800,90100,35000"
st "rst"
blo "88000,34800"
tm "WireNameMgr"
)
)
on &15
)
*281 (Wire
uid 1794,0
optionalChildren [
*282 (Ripper
uid 1832,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"67000,92000"
"68000,93000"
]
uid 1833,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,92000,68000,93000"
)
)
]
shape (OrthoPolyLine
uid 1795,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,85000,67000,94000"
pts [
"67000,85000"
"67000,94000"
]
)
start &266
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1798,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1799,0
ro 270
va (VaSet
isHidden 1
)
xt "65800,83000,67000,89800"
st "instruction"
blo "66800,89800"
tm "WireNameMgr"
)
)
on &40
)
*283 (Wire
uid 1802,0
shape (OrthoPolyLine
uid 1803,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68006,76000,89250,76000"
pts [
"68006,76000"
"89250,76000"
]
)
start &269
end &221
sat 32
eat 32
sty 1
sl "(19 DOWNTO 15)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1806,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1807,0
va (VaSet
)
xt "79000,74800,89800,76000"
st "instruction(19:15)"
blo "79000,75800"
tm "WireNameMgr"
)
)
on &40
)
*284 (Wire
uid 1810,0
shape (OrthoPolyLine
uid 1811,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68007,78000,89250,78000"
pts [
"68007,78000"
"89250,78000"
]
)
start &267
end &227
sat 32
eat 32
sty 1
sl "(24 DOWNTO 20)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1814,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1815,0
va (VaSet
)
xt "79000,76800,89800,78000"
st "instruction(24:20)"
blo "79000,77800"
tm "WireNameMgr"
)
)
on &40
)
*285 (Wire
uid 1818,0
shape (OrthoPolyLine
uid 1819,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68007,80000,89250,80000"
pts [
"68007,80000"
"89250,80000"
]
)
start &268
end &228
sat 32
eat 32
sty 1
sl "(11 DOWNTO 7)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1822,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1823,0
va (VaSet
)
xt "79000,78800,89100,80000"
st "instruction(11:7)"
blo "79000,79800"
tm "WireNameMgr"
)
)
on &40
)
*286 (Wire
uid 1826,0
shape (OrthoPolyLine
uid 1827,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68000,93000,89250,93000"
pts [
"68000,93000"
"89250,93000"
]
)
start &282
end &203
sat 32
eat 32
sty 1
sl "(31 DOWNTO 7)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1830,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1831,0
va (VaSet
)
xt "80000,91800,90100,93000"
st "instruction(31:7)"
blo "80000,92800"
tm "WireNameMgr"
)
)
on &40
)
*287 (Wire
uid 1836,0
shape (OrthoPolyLine
uid 1837,0
va (VaSet
vasetType 3
)
xt "93000,69000,93000,70250"
pts [
"93000,69000"
"93000,70250"
]
)
end &220
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1842,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1843,0
va (VaSet
)
xt "92059,67035,94259,68235"
st "clk"
blo "92059,68035"
tm "WireNameMgr"
)
)
on &16
)
*288 (Wire
uid 1844,0
shape (OrthoPolyLine
uid 1845,0
va (VaSet
vasetType 3
)
xt "96000,69000,96000,70250"
pts [
"96000,69000"
"96000,70250"
]
)
end &226
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1850,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1851,0
va (VaSet
)
xt "95000,67041,97100,68241"
st "rst"
blo "95000,68041"
tm "WireNameMgr"
)
)
on &15
)
*289 (Wire
uid 1854,0
shape (OrthoPolyLine
uid 1855,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "107750,76000,120250,76000"
pts [
"107750,76000"
"120250,76000"
]
)
start &223
end &186
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1860,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1861,0
va (VaSet
)
xt "115000,74800,117900,76000"
st "RD1"
blo "115000,75800"
tm "WireNameMgr"
)
)
on &41
)
*290 (Wire
uid 2096,0
shape (OrthoPolyLine
uid 2097,0
va (VaSet
vasetType 3
)
xt "98750,54000,100000,70250"
pts [
"98750,54000"
"100000,54000"
"100000,70250"
]
)
start &146
end &225
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2098,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2099,0
ro 270
va (VaSet
)
xt "98800,65300,100000,70000"
st "regwrite"
blo "99800,70000"
tm "WireNameMgr"
)
)
on &39
)
*291 (Wire
uid 2114,0
shape (OrthoPolyLine
uid 2115,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "105750,89000,124250,93000"
pts [
"105750,93000"
"114000,93000"
"114000,89000"
"124250,89000"
]
)
start &202
end &174
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2120,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2121,0
va (VaSet
)
xt "119000,87800,123500,89000"
st "immExt"
blo "119000,88800"
tm "WireNameMgr"
)
)
on &42
)
*292 (Wire
uid 2370,0
shape (OrthoPolyLine
uid 2371,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "49000,58000,120250,72000"
pts [
"49000,66000"
"49000,58000"
"61000,58000"
"61000,64000"
"114000,64000"
"114000,72000"
"120250,72000"
]
)
start &258
end &185
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2372,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2373,0
va (VaSet
)
xt "115000,70800,117800,72000"
st "PCu"
blo "115000,71800"
tm "WireNameMgr"
)
)
on &78
)
*293 (Wire
uid 2388,0
shape (OrthoPolyLine
uid 2389,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "114000,78000,120250,78000"
pts [
"120250,78000"
"114000,78000"
]
)
start &183
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2392,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2393,0
va (VaSet
)
xt "115000,76800,121600,78000"
st "four_zeros"
blo "115000,77800"
tm "WireNameMgr"
)
s (Text
uid 2918,0
va (VaSet
)
xt "115000,78000,115000,78000"
blo "115000,78000"
tm "SignalTypeMgr"
)
)
on &58
)
*294 (Wire
uid 2400,0
shape (OrthoPolyLine
uid 2401,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "118000,93000,124250,93000"
pts [
"124250,93000"
"118000,93000"
]
)
start &173
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2404,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2405,0
va (VaSet
)
xt "119000,91800,125600,93000"
st "four_zeros"
blo "119000,92800"
tm "WireNameMgr"
)
s (Text
uid 2921,0
va (VaSet
)
xt "119000,93000,119000,93000"
blo "119000,93000"
tm "SignalTypeMgr"
)
)
on &58
)
*295 (Wire
uid 2418,0
shape (OrthoPolyLine
uid 2419,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "118000,91000,124250,91000"
pts [
"124250,91000"
"118000,91000"
]
)
start &176
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2422,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2423,0
va (VaSet
)
xt "119000,89800,124100,91000"
st "four_four"
blo "119000,90800"
tm "WireNameMgr"
)
s (Text
uid 2924,0
va (VaSet
)
xt "119000,91000,119000,91000"
blo "119000,91000"
tm "SignalTypeMgr"
)
)
on &59
)
*296 (Wire
uid 2426,0
shape (OrthoPolyLine
uid 2427,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "112000,87000,124250,87000"
pts [
"124250,87000"
"112000,87000"
]
)
start &175
end &253
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2429,0
va (VaSet
)
xt "119000,85800,124500,87000"
st "writeData"
blo "119000,86800"
tm "WireNameMgr"
)
)
on &28
)
*297 (Wire
uid 2436,0
shape (OrthoPolyLine
uid 2437,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "125750,75000,135250,78000"
pts [
"125750,75000"
"134000,75000"
"134000,78000"
"135250,78000"
]
)
start &187
end &213
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2440,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2441,0
va (VaSet
)
xt "131000,73800,134100,75000"
st "srcA"
blo "131000,74800"
tm "WireNameMgr"
)
s (Text
uid 2925,0
va (VaSet
)
xt "131000,75000,131000,75000"
blo "131000,75000"
tm "SignalTypeMgr"
)
)
on &47
)
*298 (Wire
uid 2444,0
shape (OrthoPolyLine
uid 2445,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "129750,87000,135250,90000"
pts [
"129750,90000"
"134000,90000"
"134000,87000"
"135250,87000"
]
)
start &177
end &214
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2448,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2449,0
va (VaSet
)
xt "131000,88800,134000,90000"
st "srcB"
blo "131000,89800"
tm "WireNameMgr"
)
s (Text
uid 2926,0
va (VaSet
)
xt "131000,90000,131000,90000"
blo "131000,90000"
tm "SignalTypeMgr"
)
)
on &48
)
*299 (Wire
uid 2586,0
shape (OrthoPolyLine
uid 2587,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "169000,90000,175250,90000"
pts [
"175250,90000"
"169000,90000"
]
)
start &193
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2592,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2593,0
va (VaSet
)
xt "170000,88800,176600,90000"
st "four_zeros"
blo "170000,89800"
tm "WireNameMgr"
)
s (Text
uid 2594,0
va (VaSet
)
xt "170000,90000,170000,90000"
blo "170000,90000"
tm "SignalTypeMgr"
)
)
on &58
)
*300 (Wire
uid 2724,0
shape (OrthoPolyLine
uid 2725,0
va (VaSet
vasetType 3
)
xt "156000,79000,156000,80250"
pts [
"156000,79000"
"156000,80250"
]
)
end &64
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2728,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2729,0
va (VaSet
)
xt "155059,77035,157259,78235"
st "clk"
blo "155059,78035"
tm "WireNameMgr"
)
)
on &16
)
*301 (Wire
uid 2730,0
shape (OrthoPolyLine
uid 2731,0
va (VaSet
vasetType 3
)
xt "150000,86000,153250,86000"
pts [
"150000,86000"
"153250,86000"
]
)
end &62
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2734,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2735,0
va (VaSet
)
xt "151000,84800,153100,86000"
st "rst"
blo "151000,85800"
tm "WireNameMgr"
)
)
on &15
)
*302 (Wire
uid 2759,0
shape (OrthoPolyLine
uid 2760,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "158750,84000,175250,84000"
pts [
"158750,84000"
"175250,84000"
]
)
start &66
end &195
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 2761,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2762,0
va (VaSet
)
xt "171000,82800,175800,84000"
st "ALUOut"
blo "171000,83800"
tm "WireNameMgr"
)
)
on &50
)
*303 (Wire
uid 2765,0
optionalChildren [
*304 (BdJunction
uid 3752,0
ps "OnConnectorStrategy"
shape (Circle
uid 3753,0
va (VaSet
vasetType 1
)
xt "151600,83600,152400,84400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 2766,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "152000,76000,175250,88000"
pts [
"175250,88000"
"161000,88000"
"161000,76000"
"152000,76000"
"152000,84000"
"153250,84000"
]
)
start &196
end &65
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2767,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2768,0
va (VaSet
)
xt "170000,86800,176100,88000"
st "ALUResult"
blo "170000,87800"
tm "WireNameMgr"
)
)
on &49
)
*305 (Wire
uid 2849,0
optionalChildren [
*306 (BdJunction
uid 2859,0
ps "OnConnectorStrategy"
shape (Circle
uid 2860,0
va (VaSet
vasetType 1
)
xt "69600,100600,70400,101400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 2850,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "33000,87000,183000,101000"
pts [
"33000,101000"
"183000,101000"
"183000,87000"
"180750,87000"
]
)
start &52
end &197
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2851,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2852,0
va (VaSet
isHidden 1
)
xt "35000,99800,38600,101000"
st "result"
blo "35000,100800"
tm "WireNameMgr"
)
s (Text
uid 2934,0
va (VaSet
isHidden 1
)
xt "35000,101000,35000,101000"
blo "35000,101000"
tm "SignalTypeMgr"
)
)
on &57
)
*307 (Wire
uid 2855,0
shape (OrthoPolyLine
uid 2856,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,83000,89250,101000"
pts [
"89250,83000"
"70000,83000"
"70000,101000"
]
)
start &222
end &306
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2857,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2858,0
va (VaSet
)
xt "84250,81800,87850,83000"
st "result"
blo "84250,82800"
tm "WireNameMgr"
)
)
on &57
)
*308 (Wire
uid 3592,0
shape (OrthoPolyLine
uid 3593,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "53000,81000,54250,81000"
pts [
"53000,81000"
"54250,81000"
]
)
start &251
end &133
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3594,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3595,0
va (VaSet
isHidden 1
)
xt "50250,79800,53150,81000"
st "data"
blo "50250,80800"
tm "WireNameMgr"
)
)
on &31
)
*309 (Wire
uid 3748,0
shape (OrthoPolyLine
uid 3749,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "145750,84000,152000,84000"
pts [
"152000,84000"
"145750,84000"
]
)
start &304
end &212
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3750,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3751,0
va (VaSet
)
xt "146000,82800,152100,84000"
st "ALUResult"
blo "146000,83800"
tm "WireNameMgr"
)
)
on &49
)
*310 (Wire
uid 4056,0
shape (OrthoPolyLine
uid 4057,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "22000,66000,35000,79000"
pts [
"22000,79000"
"22000,66000"
"35000,66000"
]
)
start &243
end &73
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4058,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4059,0
va (VaSet
)
xt "32000,64800,34200,66000"
st "PC"
blo "32000,65800"
tm "WireNameMgr"
)
)
on &14
)
*311 (Wire
uid 4353,0
shape (OrthoPolyLine
uid 4354,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "170000,14000,173000,14000"
pts [
"173000,14000"
"170000,14000"
]
)
start &91
end &92
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4357,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4358,0
va (VaSet
isHidden 1
)
xt "175000,12800,180200,14000"
st "dbg_leds"
blo "175000,13800"
tm "WireNameMgr"
)
)
on &90
)
*312 (Wire
uid 4387,0
shape (OrthoPolyLine
uid 4388,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,11000,118000,11000"
pts [
"110000,11000"
"118000,11000"
]
)
end &92
sat 16
eat 1
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 4393,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4394,0
va (VaSet
)
xt "115000,9800,117300,11000"
st "adr"
blo "115000,10800"
tm "WireNameMgr"
)
s (Text
uid 4395,0
va (VaSet
)
xt "115000,11000,115000,11000"
blo "115000,11000"
tm "SignalTypeMgr"
)
)
on &27
)
*313 (Wire
uid 4396,0
shape (OrthoPolyLine
uid 4397,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,13000,118000,13000"
pts [
"110000,13000"
"118000,13000"
]
)
end &92
sat 16
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4402,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4403,0
va (VaSet
)
xt "111000,11800,117800,13000"
st "instruction"
blo "111000,12800"
tm "WireNameMgr"
)
)
on &40
)
*314 (Wire
uid 4420,0
shape (OrthoPolyLine
uid 4421,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,15000,118000,15000"
pts [
"118000,15000"
"110000,15000"
]
)
start &92
sat 1
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4426,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4427,0
va (VaSet
)
xt "112000,13800,117300,15000"
st "resultSrc"
blo "112000,14800"
tm "WireNameMgr"
)
)
on &34
)
*315 (Wire
uid 4428,0
shape (OrthoPolyLine
uid 4429,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,17000,118000,17000"
pts [
"118000,17000"
"110000,17000"
]
)
start &92
sat 1
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4434,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4435,0
va (VaSet
)
xt "112000,15800,119300,17000"
st "ALUControl"
blo "112000,16800"
tm "WireNameMgr"
)
)
on &35
)
*316 (Wire
uid 4436,0
shape (OrthoPolyLine
uid 4437,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,19000,118000,19000"
pts [
"118000,19000"
"110000,19000"
]
)
start &92
sat 1
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4442,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4443,0
va (VaSet
)
xt "112000,17800,117400,19000"
st "ALUSrcA"
blo "112000,18800"
tm "WireNameMgr"
)
)
on &37
)
*317 (Wire
uid 4444,0
shape (OrthoPolyLine
uid 4445,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,21000,118000,21000"
pts [
"118000,21000"
"110000,21000"
]
)
start &92
sat 1
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4450,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4451,0
va (VaSet
)
xt "112000,19800,117300,21000"
st "ALUSrcB"
blo "112000,20800"
tm "WireNameMgr"
)
)
on &36
)
*318 (Wire
uid 4452,0
shape (OrthoPolyLine
uid 4453,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,23000,118000,23000"
pts [
"118000,23000"
"110000,23000"
]
)
start &92
sat 1
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4458,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4459,0
va (VaSet
)
xt "112000,21800,116500,23000"
st "immSrc"
blo "112000,22800"
tm "WireNameMgr"
)
)
on &38
)
*319 (Wire
uid 4470,0
shape (OrthoPolyLine
uid 4471,0
va (VaSet
vasetType 3
)
xt "110000,25000,118000,25000"
pts [
"110000,25000"
"118000,25000"
]
)
end &92
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 4476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4477,0
va (VaSet
)
xt "112000,23800,116700,25000"
st "regwrite"
blo "112000,24800"
tm "WireNameMgr"
)
)
on &39
)
*320 (Wire
uid 4484,0
shape (OrthoPolyLine
uid 4485,0
va (VaSet
vasetType 3
)
xt "11000,42000,14000,42000"
pts [
"11000,42000"
"13000,42000"
"14000,42000"
]
)
start &96
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4488,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4489,0
va (VaSet
isHidden 1
)
xt "11000,39800,12900,41000"
st "en"
blo "11000,40800"
tm "WireNameMgr"
)
)
on &97
)
*321 (Wire
uid 4498,0
shape (OrthoPolyLine
uid 4499,0
va (VaSet
vasetType 3
)
xt "153000,88750,156000,90000"
pts [
"153000,90000"
"156000,90000"
"156000,88750"
]
)
end &63
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4504,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4505,0
va (VaSet
)
xt "154000,88800,155900,90000"
st "en"
blo "154000,89800"
tm "WireNameMgr"
)
)
on &97
)
*322 (Wire
uid 4508,0
shape (OrthoPolyLine
uid 4509,0
va (VaSet
vasetType 3
)
xt "12000,88000,15000,90000"
pts [
"12000,90000"
"15000,90000"
"15000,88000"
]
)
end &99
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4514,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4515,0
va (VaSet
)
xt "13000,88800,14900,90000"
st "en"
blo "13000,89800"
tm "WireNameMgr"
)
)
on &97
)
*323 (Wire
uid 4540,0
shape (OrthoPolyLine
uid 4541,0
va (VaSet
vasetType 3
)
xt "16000,83750,16000,85050"
pts [
"16000,85050"
"16000,83750"
]
)
start &101
end &164
sat 32
eat 32
sf 1
si 0
tg (WTG
uid 4542,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4543,0
ro 270
va (VaSet
isHidden 1
)
xt "14800,73850,16000,84050"
st "out1 : std_uLogic"
blo "15800,84050"
tm "WireNameMgr"
)
)
on &105
)
*324 (Wire
uid 4568,0
shape (OrthoPolyLine
uid 4569,0
va (VaSet
vasetType 3
)
xt "56000,75000,59000,76000"
pts [
"59000,76000"
"56000,76000"
"56000,75000"
]
)
end &107
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4572,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4573,0
va (VaSet
)
xt "57000,74800,58900,76000"
st "en"
blo "57000,75800"
tm "WireNameMgr"
)
)
on &97
)
*325 (Wire
uid 4574,0
shape (OrthoPolyLine
uid 4575,0
va (VaSet
vasetType 3
)
xt "54000,75000,54000,77000"
pts [
"54000,77000"
"54000,75000"
]
)
start &256
end &108
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4576,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4577,0
va (VaSet
)
xt "49000,75800,53500,77000"
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sat 32
eat 32
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st 0
si 0
tg (WTG
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sat 16
eat 32
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st 0
sf 1
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tg (WTG
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ps "ConnStartEndStrategy"
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sat 16
eat 32
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st 0
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va (VaSet
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sat 16
eat 32
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st 0
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tm "WireNameMgr"
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start &230
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sat 32
eat 32
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stc 0
st 0
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start &231
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sat 32
eat 32
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stc 0
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tg (WTG
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ro 270
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tm "WireNameMgr"
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on &116
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