-- VHDL Entity WaveformGenerator.waveformGen.symbol
--
-- Created:
--          by - francois.corthay.UNKNOWN (WEA20303)
--          at - 17:19:13 06.03.2019
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

ENTITY waveformGen IS
    GENERIC( 
        phaseBitNb  : positive := 16;
        signalBitNb : positive := 16
    );
    PORT( 
        clock    : IN     std_ulogic;
        en       : IN     std_ulogic;
        reset    : IN     std_ulogic;
        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
        polygon  : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        sawtooth : OUT    unsigned (phaseBitNb-1 DOWNTO 0);
        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
    );

-- Declarations

END waveformGen ;

