-- VHDL Entity WaveformGenerator_test.waveformGen_tester.interface
--
-- Created:
--          by - axel.amand.UNKNOWN (WE7860)
--          at - 14:39:31 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

ENTITY waveformGen_tester IS
    GENERIC( 
        bitNb          : positive := 16;
        clockFrequency : real     := 60.0E6
    );
    PORT( 
        clock : OUT    std_ulogic;
        en    : OUT    std_ulogic;
        reset : OUT    std_ulogic;
        step  : OUT    unsigned (bitNb-1 DOWNTO 0)
    );

-- Declarations

END waveformGen_tester ;

