DocumentHdrVersion "1.1"
Header (DocumentHdr
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dialect 11
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duName "pll"
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version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
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)
tg (CPTG
uid 243,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 244,0
va (VaSet
font "Verdana,12,0"
)
xt "47200,13300,49000,14700"
st "Q"
ju 2
blo "49000,14500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 220,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "44000,12000,50000,20000"
)
showPorts 0
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 221,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*33 (Text
uid 222,0
va (VaSet
)
xt "48600,19700,52200,20900"
st "Board"
blo "48600,20700"
tm "BdLibraryNameMgr"
)
*34 (Text
uid 223,0
va (VaSet
)
xt "48600,20700,51300,21900"
st "DFF"
blo "48600,21700"
tm "CptNameMgr"
)
*35 (Text
uid 224,0
va (VaSet
)
xt "48600,21700,51600,22900"
st "I_dff"
blo "48600,22700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 225,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 226,0
text (MLText
uid 227,0
va (VaSet
)
xt "21000,9000,21000,9000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*36 (SaComponent
uid 245,0
optionalChildren [
*37 (CptPort
uid 254,0
optionalChildren [
*38 (Circle
uid 259,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "54092,13546,55000,14454"
radius 454
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 255,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "53342,13625,54092,14375"
)
tg (CPTG
uid 256,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 257,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "55000,13500,57700,14900"
st "in1"
blo "55000,14700"
)
s (Text
uid 258,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "55000,14900,55000,14900"
blo "55000,14900"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*39 (CptPort
uid 260,0
ps "OnEdgeStrategy"
shape (Triangle
uid 261,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "60000,13625,60750,14375"
)
tg (CPTG
uid 262,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 263,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "56050,13500,59750,14900"
st "out1"
ju 2
blo "59750,14700"
)
s (Text
uid 264,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "59750,14900,59750,14900"
ju 2
blo "59750,14900"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 246,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "55000,11000,60000,17000"
)
showPorts 0
oxt "23000,4000,28000,10000"
ttg (MlTextGroup
uid 247,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*40 (Text
uid 248,0
va (VaSet
)
xt "56460,16700,60060,17900"
st "Board"
blo "56460,17700"
tm "BdLibraryNameMgr"
)
*41 (Text
uid 249,0
va (VaSet
)
xt "56460,17700,62860,18900"
st "inverterIn"
blo "56460,18700"
tm "CptNameMgr"
)
*42 (Text
uid 250,0
va (VaSet
)
xt "56460,18700,60460,19900"
st "I_inv2"
blo "56460,19700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 251,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 252,0
text (MLText
uid 253,0
va (VaSet
)
xt "55000,17400,55000,17400"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*43 (SaComponent
uid 265,0
optionalChildren [
*44 (CptPort
uid 274,0
ps "OnEdgeStrategy"
shape (Triangle
uid 275,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "66250,9625,67000,10375"
)
tg (CPTG
uid 276,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 277,0
va (VaSet
)
xt "68000,9400,71400,10600"
st "clock"
blo "68000,10400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
)
)
)
*45 (CptPort
uid 278,0
ps "OnEdgeStrategy"
shape (Triangle
uid 279,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "83000,9625,83750,10375"
)
tg (CPTG
uid 280,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 281,0
va (VaSet
)
xt "75400,9400,82000,10600"
st "triggerOut"
ju 2
blo "82000,10400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "triggerOut"
t "std_ulogic"
o 3
)
)
)
*46 (CptPort
uid 282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 283,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "83000,7625,83750,8375"
)
tg (CPTG
uid 284,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 285,0
va (VaSet
)
xt "78800,7400,82000,8600"
st "xOut"
ju 2
blo "82000,8400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "xOut"
t "std_ulogic"
o 4
)
)
)
*47 (CptPort
uid 286,0
ps "OnEdgeStrategy"
shape (Triangle
uid 287,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "83000,5625,83750,6375"
)
tg (CPTG
uid 288,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 289,0
va (VaSet
)
xt "78800,5400,82000,6600"
st "yOut"
ju 2
blo "82000,6400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "yOut"
t "std_ulogic"
o 5
)
)
)
*48 (CptPort
uid 290,0
ps "OnEdgeStrategy"
shape (Triangle
uid 291,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "66250,11625,67000,12375"
)
tg (CPTG
uid 292,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 293,0
va (VaSet
)
xt "68000,11500,71300,12700"
st "reset"
blo "68000,12500"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
)
)
)
]
shape (Rectangle
uid 266,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "67000,2000,83000,14000"
)
oxt "32000,10000,48000,22000"
ttg (MlTextGroup
uid 267,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*49 (Text
uid 268,0
va (VaSet
font "Verdana,9,1"
)
xt "67600,13800,72800,15000"
st "Lissajous"
blo "67600,14800"
tm "BdLibraryNameMgr"
)
*50 (Text
uid 269,0
va (VaSet
font "Verdana,9,1"
)
xt "67600,14700,78100,15900"
st "lissajousGenerator"
blo "67600,15700"
tm "CptNameMgr"
)
*51 (Text
uid 270,0
va (VaSet
font "Verdana,9,1"
)
xt "67600,15600,71700,16800"
st "I_main"
blo "67600,16600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 271,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 272,0
text (MLText
uid 273,0
va (VaSet
)
xt "67000,17600,90500,22400"
st "signalBitNb = signalBitNb    ( positive )  
phaseBitNb  = phaseBitNb     ( positive )  
stepX       = stepX          ( positive )  
stepY       = stepY          ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "phaseBitNb"
type "positive"
value "phaseBitNb"
)
(GiElement
name "stepX"
type "positive"
value "stepX"
)
(GiElement
name "stepY"
type "positive"
value "stepY"
)
]
)
connectByName 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*52 (PortIoOut
uid 294,0
shape (CompositeShape
uid 295,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 296,0
sl 0
ro 270
xt "91500,9625,93000,10375"
)
(Line
uid 297,0
sl 0
ro 270
xt "91000,10000,91500,10000"
pts [
"91000,10000"
"91500,10000"
]
)
]
)
tg (WTG
uid 298,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 299,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "94000,9300,102100,10700"
st "triggerOut"
blo "94000,10500"
tm "WireNameMgr"
)
)
)
*53 (PortIoOut
uid 300,0
shape (CompositeShape
uid 301,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 302,0
sl 0
ro 270
xt "91500,7625,93000,8375"
)
(Line
uid 303,0
sl 0
ro 270
xt "91000,8000,91500,8000"
pts [
"91000,8000"
"91500,8000"
]
)
]
)
tg (WTG
uid 304,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 305,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "94000,7300,97800,8700"
st "xOut"
blo "94000,8500"
tm "WireNameMgr"
)
)
)
*54 (PortIoOut
uid 306,0
shape (CompositeShape
uid 307,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 308,0
sl 0
ro 270
xt "91500,5625,93000,6375"
)
(Line
uid 309,0
sl 0
ro 270
xt "91000,6000,91500,6000"
pts [
"91000,6000"
"91500,6000"
]
)
]
)
tg (WTG
uid 310,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 311,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "94000,5300,97800,6700"
st "yOut"
blo "94000,6500"
tm "WireNameMgr"
)
)
)
*55 (Net
uid 356,0
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
declText (MLText
uid 357,0
va (VaSet
)
xt "2000,9000,15100,10200"
st "clock        : std_ulogic
"
)
)
*56 (Net
uid 358,0
decl (Decl
n "triggerOut"
t "std_ulogic"
o 2
suid 2,0
)
declText (MLText
uid 359,0
va (VaSet
)
xt "2000,11400,16100,12600"
st "triggerOut   : std_ulogic
"
)
)
*57 (Net
uid 360,0
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
declText (MLText
uid 361,0
va (VaSet
)
xt "2000,23400,19500,24600"
st "SIGNAL reset        : std_ulogic
"
)
)
*58 (Net
uid 364,0
decl (Decl
n "reset_N"
t "std_ulogic"
o 5
suid 5,0
)
declText (MLText
uid 365,0
va (VaSet
)
xt "2000,10200,15800,11400"
st "reset_N      : std_ulogic
"
)
)
*59 (Net
uid 366,0
decl (Decl
n "xOut"
t "std_ulogic"
o 6
suid 6,0
)
declText (MLText
uid 367,0
va (VaSet
)
xt "2000,12600,15200,13800"
st "xOut         : std_ulogic
"
)
)
*60 (Net
uid 368,0
decl (Decl
n "resetSynch"
t "std_ulogic"
o 7
suid 7,0
)
declText (MLText
uid 369,0
va (VaSet
)
xt "2000,24600,21100,25800"
st "SIGNAL resetSynch   : std_ulogic
"
)
)
*61 (Net
uid 370,0
decl (Decl
n "logic1"
t "std_uLogic"
o 8
suid 8,0
)
declText (MLText
uid 371,0
va (VaSet
)
xt "2000,22200,20000,23400"
st "SIGNAL logic1       : std_uLogic
"
)
)
*62 (Net
uid 372,0
decl (Decl
n "yOut"
t "std_ulogic"
o 9
suid 9,0
)
declText (MLText
uid 373,0
va (VaSet
)
xt "2000,13800,15200,15000"
st "yOut         : std_ulogic
"
)
)
*63 (Net
uid 380,0
lang 11
decl (Decl
n "clkSys"
t "std_ulogic"
o 10
suid 11,0
)
declText (MLText
uid 381,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20600,19500,21400"
st "SIGNAL clkSys       : std_ulogic
"
)
)
*64 (HdlText
uid 382,0
optionalChildren [
*65 (EmbeddedText
uid 387,0
commentText (CommentText
uid 388,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 389,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "22000,5000,31000,7000"
)
oxt "0,0,18000,5000"
text (MLText
uid 390,0
va (VaSet
)
xt "22200,5200,30400,6400"
st "
logic0 <= '0';
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 9000
)
)
)
]
shape (Rectangle
uid 383,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "22000,4000,32000,8000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 384,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
uid 385,0
va (VaSet
)
xt "24400,8000,27000,9200"
st "eb6"
blo "24400,9000"
tm "HdlTextNameMgr"
)
*67 (Text
uid 386,0
va (VaSet
)
xt "24400,9000,25800,10200"
st "6"
blo "24400,10000"
tm "HdlTextNumberMgr"
)
]
)
)
*68 (Net
uid 411,0
lang 11
decl (Decl
n "logic0"
t "std_ulogic"
o 11
suid 13,0
)
declText (MLText
uid 412,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,21400,19500,22200"
st "SIGNAL logic0       : std_ulogic
"
)
)
*69 (Net
uid 464,0
decl (Decl
n "resetSynch_N"
t "std_ulogic"
o 4
suid 14,0
)
declText (MLText
uid 465,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,25800,19500,26600"
st "SIGNAL resetSynch_N : std_ulogic
"
)
)
*70 (Wire
uid 312,0
shape (OrthoPolyLine
uid 313,0
va (VaSet
vasetType 3
)
xt "26000,3000,38250,3000"
pts [
"26000,3000"
"38250,3000"
]
)
start &14
end &10
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 314,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 315,0
va (VaSet
font "Verdana,12,0"
)
xt "26000,1600,29800,3000"
st "clock"
blo "26000,2800"
tm "WireNameMgr"
)
)
on &55
)
*71 (Wire
uid 316,0
shape (OrthoPolyLine
uid 317,0
va (VaSet
vasetType 3
)
xt "83750,6000,91000,6000"
pts [
"91000,6000"
"83750,6000"
]
)
start &54
end &47
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 318,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 319,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,4600,89800,6000"
st "yOut"
blo "86000,5800"
tm "WireNameMgr"
)
)
on &62
)
*72 (Wire
uid 320,0
shape (OrthoPolyLine
uid 321,0
va (VaSet
vasetType 3
)
xt "38000,20000,47000,22000"
pts [
"38000,22000"
"47000,22000"
"47000,20000"
]
)
start &23
end &31
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 322,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 323,0
va (VaSet
font "Verdana,12,0"
)
xt "39000,20600,43100,22000"
st "reset"
blo "39000,21800"
tm "WireNameMgr"
)
)
on &57
)
*73 (Wire
uid 324,0
shape (OrthoPolyLine
uid 325,0
va (VaSet
vasetType 3
)
xt "83750,10000,91000,10000"
pts [
"91000,10000"
"83750,10000"
]
)
start &52
end &45
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 327,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,8600,94100,10000"
st "triggerOut"
blo "86000,9800"
tm "WireNameMgr"
)
)
on &56
)
*74 (Wire
uid 328,0
shape (OrthoPolyLine
uid 329,0
va (VaSet
vasetType 3
)
xt "42000,18000,44000,18000"
pts [
"42000,18000"
"44000,18000"
]
)
end &29
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 332,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 333,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,16600,43800,18000"
st "clock"
blo "40000,17800"
tm "WireNameMgr"
)
)
on &55
)
*75 (Wire
uid 334,0
shape (OrthoPolyLine
uid 335,0
va (VaSet
vasetType 3
)
xt "50000,14000,54092,14000"
pts [
"50000,14000"
"54092,14000"
]
)
start &32
end &37
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 336,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 337,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,12600,59300,14000"
st "resetSynch_N"
blo "49000,13800"
tm "WireNameMgr"
)
)
on &69
)
*76 (Wire
uid 338,0
shape (OrthoPolyLine
uid 339,0
va (VaSet
vasetType 3
)
xt "39000,14000,44000,14000"
pts [
"44000,14000"
"39000,14000"
]
)
start &28
end &16
sat 32
eat 2
stc 0
sf 1
si 0
tg (WTG
uid 342,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 343,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,12600,44400,14000"
st "logic1"
blo "40000,13800"
tm "WireNameMgr"
)
)
on &61
)
*77 (Wire
uid 344,0
shape (OrthoPolyLine
uid 345,0
va (VaSet
vasetType 3
)
xt "83750,8000,91000,8000"
pts [
"91000,8000"
"83750,8000"
]
)
start &53
end &46
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 346,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 347,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,6600,89800,8000"
st "xOut"
blo "86000,7800"
tm "WireNameMgr"
)
)
on &59
)
*78 (Wire
uid 348,0
shape (OrthoPolyLine
uid 349,0
va (VaSet
vasetType 3
)
xt "27000,22000,32092,22000"
pts [
"27000,22000"
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sat 32
eat 32
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st 0
sf 1
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
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va (VaSet
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tm "WireNameMgr"
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start &4
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sat 32
eat 32
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sf 1
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tg (WTG
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ps "ConnStartEndStrategy"
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va (VaSet
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sat 2
eat 32
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tg (WTG
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va (VaSet
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ps "OnConnectorStrategy"
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sat 32
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st 0
sf 1
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stg "STSignalDisplayStrategy"
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start &7
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sat 32
eat 32
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st 0
sf 1
si 0
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
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va (VaSet
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on &68
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visOptions (mwParamsVisibilityOptions
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text (MLText
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portVis (PortSigDisplay
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ttg (MlTextGroup
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tm "InstanceNameMgr"
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ttg (MlTextGroup
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tm "InstanceNameMgr"
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ga (GenericAssociation
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xt "0,0,8000,10000"
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tm "HdlTextNameMgr"
)
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tm "HdlTextNumberMgr"
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viewicon (ZoomableIcon
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va (VaSet
vasetType 1
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)
xt "0,0,1500,1500"
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)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
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Text
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va (VaSet
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)
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xt "-400,-400,400,400"
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)
)
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ro 270
xt "500,-375,2000,375"
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defaultPortIoInOut (PortIoInOut
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va (VaSet
vasetType 1
fg "0,0,32768"
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xt "500,-375,2000,375"
)
(Line
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xt "0,0,500,0"
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tg (WTG
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tm "WireNameMgr"
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sat 32
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tg (WTG
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eat 32
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tg (WTG
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lineWidth 3
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xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
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xt "0,-1300,11000,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1850,1650"
)
num (Text
va (VaSet
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xt "250,250,1650,1450"
st "1"
blo "250,1250"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
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stg "VerticalLayoutStrategy"
textVec [
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xt "11200,20000,22000,21200"
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blo "11200,21000"
)
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xt "0,0,750,750"
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tg (CPTG
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stg "VerticalLayoutStrategy"
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blo "0,1750"
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)
thePort (LogicalPort
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decl (Decl
n "Port"
t ""
o 0
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)
)
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vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
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tg (CPTG
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stg "VerticalLayoutStrategy"
f (Text
va (VaSet
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st "Port"
blo "0,1750"
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)
thePort (LogicalPort
lang 11
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
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)
archDeclarativeBlock (BdArchDeclBlock
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stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
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blo "0,7600"
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portLabel (Text
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va (VaSet
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xt "0,7800,3700,9000"
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uid 4,0
va (VaSet
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xt "0,15000,5200,16200"
st "Pre User:"
blo "0,16000"
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preUserText (MLText
uid 5,0
va (VaSet
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xt "2000,16200,22000,19400"
st "constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 17;
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tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
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xt "0,19400,9500,20600"
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blo "0,20400"
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uid 7,0
va (VaSet
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xt "0,6600,6400,7800"
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)
postUserText (MLText
uid 8,0
va (VaSet
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font "Courier New,8,0"
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xt "0,6600,0,6600"
tm "BdDeclarativeTextMgr"
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ldm (LogicalDM
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usingSuid 1
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uid 54,0
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*122 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*123 (GroupColHdr
tm "GroupColHdrMgr"
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*124 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
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*125 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
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*126 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
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*127 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
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*128 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
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*129 (EolColHdr
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uid 429,0
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m 4
decl (Decl
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uid 431,0
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m 4
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o 11
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pdm (PhysicalDM
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editShortBounds 1
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genericsCommonDM (CommonDM
ldm (LogicalDM
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uid 83,0
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*170 (RowExpandColHdr
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uid 82,0
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activeModelName "BlockDiag"
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