DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
(DmPackageRef
library "AhbLite"
unitName "ahbLite"
)
]
libraryRefs [
"ieee"
"AhbLite"
]
)
version "24.1"
appVersion "2009.2 (Build 10)"
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]
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fixedCol 3
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uid 334,0
type 1
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VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahb@gpio\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahb@gpio\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "asm_file"
value "nanoTest.asm"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahb@gpio"
)
(vvPair
variable "d_logical"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahbGpio"
)
(vvPair
variable "date"
value "03.03.2015"
)
(vvPair
variable "day"
value "mar."
)
(vvPair
variable "day_long"
value "mardi"
)
(vvPair
variable "dd"
value "03"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "ahbGpio"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE3673"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "AhbLiteComponents"
)
(vvPair
variable "library_downstream_Concatenation"
value "U:/ELN_Board/Synthesis"
)
(vvPair
variable "library_downstream_Generic_1_file"
value "U:\\ELN_Board\\Synthesis"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/../NanoBlaze/designcheck"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Libs/AhbLiteComponents/work"
)
(vvPair
variable "library_downstream_SpyGlass"
value "U:\\ELN_Board\\Synthesis"
)
(vvPair
variable "mm"
value "03"
)
(vvPair
variable "module_name"
value "ahbGpio"
)
(vvPair
variable "month"
value "mars"
)
(vvPair
variable "month_long"
value "mars"
)
(vvPair
variable "p"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahb@gpio\\symbol.sb"
)
(vvPair
variable "p_logical"
value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahbGpio\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds-beamer"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$ISE_SCRATCH_WORK_DIR"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME\\win32"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "13:18:00"
)
(vvPair
variable "unit"
value "ahbGpio"
)
(vvPair
variable "user"
value "francois"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2015"
)
(vvPair
variable "yy"
value "15"
)
]
)
LanguageMgr "VhdlLangMgr"
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shape (Triangle
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dt (MLText
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xt "2000,11400,33500,12200"
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xt "2000,17800,35500,18600"
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"
)
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m 1
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
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)
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xt "2000,16200,19000,17000"
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"
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tg (CPTG
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xt "48000,23300,53100,24700"
st "hTrans"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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)
xt "2000,14600,36000,15400"
st "hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 2
suid 2059,0
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
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fg "0,65535,0"
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xt "46250,31625,47000,32375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
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)
xt "48000,31300,53500,32700"
st "hReady"
blo "48000,32500"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
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)
xt "2000,18600,19000,19400"
st "hReady   : OUT    std_uLogic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_uLogic"
o 7
suid 2061,0
)
)
)
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uid 2509,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46250,33625,47000,34375"
)
tg (CPTG
uid 2511,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
font "Verdana,12,0"
)
xt "48000,33300,52700,34700"
st "hResp"
blo "48000,34500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2513,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,19400,19000,20200"
st "hResp    : OUT    std_uLogic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_uLogic"
o 9
suid 2062,0
)
)
)
*87 (CptPort
uid 2514,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2690,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46250,37625,47000,38375"
)
tg (CPTG
uid 2516,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2517,0
va (VaSet
font "Verdana,12,0"
)
xt "48000,37300,51500,38700"
st "hClk"
blo "48000,38500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2518,0
va (VaSet
font "Courier New,8,0"
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