--
-- VHDL Architecture Lissajous_test.lissajousGenerator_test.struct
--
-- Created:
--          by - axel.amand.UNKNOWN (WE7860)
--          at - 14:48:46 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

LIBRARY Lissajous;
LIBRARY Lissajous_test;
LIBRARY WaveformGenerator;

ARCHITECTURE struct OF lissajousGenerator_test IS

    -- Architecture declarations
    constant signalBitNb: positive := 16;
    constant phaseBitNb: positive := 17;
    constant stepX: positive := 2;
    constant stepY: positive := 3;
    constant lowpassShiftBitNb: positive := 8;
    constant clockFrequency: real := 60.0E6;
    --constant clockFrequency: real := 66.0E6;

    -- Internal signal declarations
    SIGNAL clock      : std_ulogic;
    SIGNAL reset      : std_ulogic;
    SIGNAL triggerOut : std_ulogic;
    SIGNAL xLowapss   : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL xParallel  : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL xSerial    : std_ulogic;
    SIGNAL yLowpass   : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL yParallel  : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL ySerial    : std_ulogic;


    -- Component Declarations
    COMPONENT lissajousGenerator
    GENERIC (
        signalBitNb : positive := 16;
        phaseBitNb  : positive := 16;
        stepX       : positive := 1;
        stepY       : positive := 1
    );
    PORT (
        clock      : IN     std_ulogic ;
        reset      : IN     std_ulogic ;
        triggerOut : OUT    std_ulogic ;
        xOut       : OUT    std_ulogic ;
        yOut       : OUT    std_ulogic 
    );
    END COMPONENT;
    COMPONENT lissajousGenerator_tester
    GENERIC (
        signalBitNb    : positive := 16;
        clockFrequency : real     := 60.0E6
    );
    PORT (
        triggerOut : IN     std_ulogic ;
        xLowapss   : IN     unsigned (signalBitNb-1 DOWNTO 0);
        xSerial    : IN     std_ulogic ;
        yLowpass   : IN     unsigned (signalBitNb-1 DOWNTO 0);
        ySerial    : IN     std_ulogic ;
        clock      : OUT    std_ulogic ;
        reset      : OUT    std_ulogic 
    );
    END COMPONENT;
    COMPONENT lowpass
    GENERIC (
        signalBitNb : positive := 16;
        shiftBitNb  : positive := 12
    );
    PORT (
        lowpassOut : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        clock      : IN     std_ulogic ;
        reset      : IN     std_ulogic ;
        lowpassIn  : IN     unsigned (signalBitNb-1 DOWNTO 0)
    );
    END COMPONENT;

    -- Optional embedded configurations
    -- pragma synthesis_off
    FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
    FOR ALL : lissajousGenerator_tester USE ENTITY Lissajous_test.lissajousGenerator_tester;
    FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
    -- pragma synthesis_on


BEGIN
    -- Architecture concurrent statements
    -- HDL Embedded Text Block 1 eb1
    xParallel <= (others => xSerial);
    yParallel <= (others => ySerial);


    -- Instance port mappings.
    I_DUT : lissajousGenerator
        GENERIC MAP (
            signalBitNb => signalBitNb,
            phaseBitNb  => phaseBitNb,
            stepX       => stepX,
            stepY       => stepY
        )
        PORT MAP (
            clock      => clock,
            reset      => reset,
            triggerOut => triggerOut,
            xOut       => xSerial,
            yOut       => ySerial
        );
    I_tester : lissajousGenerator_tester
        GENERIC MAP (
            signalBitNb    => signalBitNb,
            clockFrequency => clockFrequency
        )
        PORT MAP (
            triggerOut => triggerOut,
            xLowapss   => xLowapss,
            xSerial    => xSerial,
            yLowpass   => yLowpass,
            ySerial    => ySerial,
            clock      => clock,
            reset      => reset
        );
    I_filtX : lowpass
        GENERIC MAP (
            signalBitNb => signalBitNb,
            shiftBitNb  => lowpassShiftBitNb
        )
        PORT MAP (
            lowpassOut => xLowapss,
            clock      => clock,
            reset      => reset,
            lowpassIn  => xParallel
        );
    I_filty : lowpass
        GENERIC MAP (
            signalBitNb => signalBitNb,
            shiftBitNb  => lowpassShiftBitNb
        )
        PORT MAP (
            lowpassOut => yLowpass,
            clock      => clock,
            reset      => reset,
            lowpassIn  => yParallel
        );

END struct;
