-- VHDL Entity Lissajous_test.lissajousGenerator_tester.interface
--
-- Created:
--          by - axel.amand.UNKNOWN (WE7860)
--          at - 14:48:11 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

ENTITY lissajousGenerator_tester IS
    GENERIC( 
        signalBitNb    : positive := 16;
        clockFrequency : real     := 60.0E6
    );
    PORT( 
        triggerOut : IN     std_ulogic;
        xLowapss   : IN     unsigned (signalBitNb-1 DOWNTO 0);
        xSerial    : IN     std_ulogic;
        yLowpass   : IN     unsigned (signalBitNb-1 DOWNTO 0);
        ySerial    : IN     std_ulogic;
        clock      : OUT    std_ulogic;
        reset      : OUT    std_ulogic
    );

-- Declarations

END lissajousGenerator_tester ;

