--
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
--
-- Created:
--          by - axel.amand.UNKNOWN (WE7860)
--          at - 17:45:49 01.05.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

LIBRARY Board;
LIBRARY Lattice;
LIBRARY Lissajous;

ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS

    -- Architecture declarations
    constant signalBitNb: positive := 16;
    constant phaseBitNb: positive := 17;
    constant stepX: positive := 3;
    constant stepY: positive := 4;

    -- Internal signal declarations
    SIGNAL clkSys       : std_ulogic;
    SIGNAL logic0       : std_ulogic;
    SIGNAL logic1       : std_uLogic;
    SIGNAL reset        : std_ulogic;
    SIGNAL resetSynch   : std_ulogic;
    SIGNAL resetSynch_N : std_ulogic;


    -- Component Declarations
    COMPONENT DFF
    PORT (
        CLK : IN     std_uLogic ;
        CLR : IN     std_uLogic ;
        D   : IN     std_uLogic ;
        Q   : OUT    std_uLogic 
    );
    END COMPONENT;
    COMPONENT inverterIn
    PORT (
        in1  : IN     std_uLogic ;
        out1 : OUT    std_uLogic 
    );
    END COMPONENT;
    COMPONENT pll
    PORT (
        clkIn100M : IN     std_ulogic;
        en10M     : IN     std_ulogic;
        en50M     : IN     std_ulogic;
        en75M     : IN     std_ulogic;
        clk10MHz  : OUT    std_ulogic;
        clk50MHz  : OUT    std_ulogic;
        clk60MHz  : OUT    std_ulogic;
        clk75MHz  : OUT    std_ulogic;
        pllLocked : OUT    std_ulogic
    );
    END COMPONENT;
    COMPONENT lissajousGenerator
    GENERIC (
        signalBitNb : positive := 16;
        phaseBitNb  : positive := 16;
        stepX       : positive := 1;
        stepY       : positive := 1
    );
    PORT (
        clock      : IN     std_ulogic ;
        reset      : IN     std_ulogic ;
        triggerOut : OUT    std_ulogic ;
        xOut       : OUT    std_ulogic ;
        yOut       : OUT    std_ulogic 
    );
    END COMPONENT;

    -- Optional embedded configurations
    -- pragma synthesis_off
    FOR ALL : DFF USE ENTITY Board.DFF;
    FOR ALL : inverterIn USE ENTITY Board.inverterIn;
    FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
    FOR ALL : pll USE ENTITY Lattice.pll;
    -- pragma synthesis_on


BEGIN
    -- Architecture concurrent statements
    -- HDL Embedded Text Block 5 eb5
    logic1 <= '1';

    -- HDL Embedded Text Block 6 eb6
    logic0 <= '0';


    -- Instance port mappings.
    I_dff : DFF
        PORT MAP (
            CLK => clock,
            CLR => reset,
            D   => logic1,
            Q   => resetSynch_N
        );
    I_inv1 : inverterIn
        PORT MAP (
            in1  => reset_N,
            out1 => reset
        );
    I_inv2 : inverterIn
        PORT MAP (
            in1  => resetSynch_N,
            out1 => resetSynch
        );
    U_pll : pll
        PORT MAP (
            clkIn100M => clock,
            en75M     => logic0,
            en50M     => logic0,
            en10M     => logic0,
            clk60MHz  => clkSys,
            clk75MHz  => OPEN,
            clk50MHz  => OPEN,
            clk10MHz  => OPEN,
            pllLocked => OPEN
        );
    I_main : lissajousGenerator
        GENERIC MAP (
            signalBitNb => signalBitNb,
            phaseBitNb  => phaseBitNb,
            stepX       => stepX,
            stepY       => stepY
        )
        PORT MAP (
            clock      => clkSys,
            reset      => resetSynch,
            triggerOut => triggerOut,
            xOut       => xOut,
            yOut       => yOut
        );

END masterVersion;
