--
-- VHDL Architecture Morse.morseEncoder.struct
--
-- Created:
--          by - axel.amand.UNKNOWN (WE7860)
--          at - 14:50:20 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

LIBRARY Memory;
LIBRARY Morse;
LIBRARY RS232;

ARCHITECTURE struct OF morseEncoder IS

    -- Architecture declarations
    constant fifoDepth : positive := 100;

    -- Internal signal declarations
    SIGNAL characterReg   : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0);
    SIGNAL characterIn    : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0);
    SIGNAL characterValid : std_ulogic;
    SIGNAL morseOut       : std_ulogic;
    SIGNAL tone           : std_ulogic;
    SIGNAL charNotReady   : std_ulogic;
    SIGNAL readChar       : std_ulogic;


    -- Component Declarations
    COMPONENT FIFO_bram
    GENERIC (
        dataBitNb : positive := 8;
        depth     : positive := 8
    );
    PORT (
        write   : IN     std_ulogic ;
        clock   : IN     std_ulogic ;
        reset   : IN     std_ulogic ;
        dataOut : OUT    std_ulogic_vector (dataBitNb-1 DOWNTO 0);
        read    : IN     std_ulogic ;
        dataIn  : IN     std_ulogic_vector (dataBitNb-1 DOWNTO 0);
        empty   : OUT    std_ulogic ;
        full    : OUT    std_ulogic 
    );
    END COMPONENT;
    COMPONENT charToMorse
    GENERIC (
        characterBitNb  : positive := 8;
        unitCountDivide : positive := 10E3
    );
    PORT (
        morseOut     : OUT    std_ulogic ;
        clock        : IN     std_ulogic ;
        reset        : IN     std_ulogic ;
        charIn       : IN     std_ulogic_vector (characterBitNb-1 DOWNTO 0);
        readChar     : OUT    std_ulogic ;
        charNotReady : IN     std_ulogic 
    );
    END COMPONENT;
    COMPONENT toneGenerator
    GENERIC (
        toneDivide : positive := 100E3
    );
    PORT (
        tone  : OUT    std_ulogic ;
        clock : IN     std_ulogic ;
        reset : IN     std_ulogic 
    );
    END COMPONENT;
    COMPONENT serialPortReceiver
    GENERIC (
        dataBitNb      : positive := 8;
        baudRateDivide : positive := 2083
    );
    PORT (
        RxD       : IN     std_ulogic ;
        clock     : IN     std_ulogic ;
        reset     : IN     std_ulogic ;
        dataOut   : OUT    std_ulogic_vector (dataBitNb-1 DOWNTO 0);
        dataValid : OUT    std_ulogic 
    );
    END COMPONENT;

    -- Optional embedded configurations
    -- pragma synthesis_off
    FOR ALL : FIFO_bram USE ENTITY Memory.FIFO_bram;
    FOR ALL : charToMorse USE ENTITY Morse.charToMorse;
    FOR ALL : serialPortReceiver USE ENTITY RS232.serialPortReceiver;
    FOR ALL : toneGenerator USE ENTITY Morse.toneGenerator;
    -- pragma synthesis_on


BEGIN
    -- Architecture concurrent statements
    -- HDL Embedded Text Block 1 eb1
    morseCode <= morseOut and tone;


    -- Instance port mappings.
    I_FIFO : FIFO_bram
        GENERIC MAP (
            dataBitNb => uartDataBitNb,
            depth     => fifoDepth
        )
        PORT MAP (
            write   => characterValid,
            clock   => clock,
            reset   => reset,
            dataOut => characterReg,
            read    => readChar,
            dataIn  => characterIn,
            empty   => charNotReady,
            full    => OPEN
        );
    I_enc : charToMorse
        GENERIC MAP (
            characterBitNb  => uartDataBitNb,
            unitCountDivide => integer(clockFrequency*unitDuration + 0.5)
        )
        PORT MAP (
            morseOut     => morseOut,
            clock        => clock,
            reset        => reset,
            charNotReady => charNotReady,
            charIn       => characterReg,
            readChar     => readChar
        );
    I_tone : toneGenerator
        GENERIC MAP (
            toneDivide => integer(clockFrequency/toneFrequency + 0.5)
        )
        PORT MAP (
            tone  => tone,
            clock => clock,
            reset => reset
        );
    I_UART : serialPortReceiver
        GENERIC MAP (
            dataBitNb      => uartDataBitNb,
            baudRateDivide => integer(clockFrequency/uartBaudRate + 0.5)
        )
        PORT MAP (
            RxD       => RxD,
            clock     => clock,
            reset     => reset,
            dataOut   => characterIn,
            dataValid => characterValid
        );

END struct;
