27 lines
547 B
Plaintext
27 lines
547 B
Plaintext
-- VHDL Entity VHD.ex_19_1_4.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 12:57:27 03/27/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY ex_19_1_4 IS
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PORT(
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A : IN std_ulogic;
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B : IN std_ulogic;
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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en : OUT std_ulogic;
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dir : OUT std_ulogic
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);
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-- Declarations
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END ex_19_1_4 ;
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