86 lines
1.8 KiB
VHDL
86 lines
1.8 KiB
VHDL
--
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-- VHDL Architecture VHD_test.tb_24_1_2.struct
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--
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-- Created:
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-- by - remy.borgeat.UNKNOWN (WE10993)
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-- at - 15:01:25 20.03.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.ALL;
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LIBRARY VHD;
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ARCHITECTURE struct OF tb_24_1_2 IS
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-- Architecture declarations
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constant pwmFrequency : real := 1.0E6;
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constant pwmPeriod : time := (1.0/pwmFrequency) * 1 sec;
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signal sPwm : std_uLogic := '1';
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-- Internal signal declarations
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SIGNAL motorOn : std_ulogic;
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SIGNAL pwm : std_ulogic;
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SIGNAL right_left : std_ulogic;
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SIGNAL side1 : std_ulogic;
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SIGNAL side2 : std_ulogic;
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-- Component Declarations
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COMPONENT ex_24_1_2
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PORT (
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motorOn : IN std_ulogic ;
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side1 : OUT std_ulogic ;
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right_left : IN std_ulogic ;
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pwm : IN std_ulogic ;
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side2 : OUT std_ulogic
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : ex_24_1_2 USE ENTITY VHD.ex_24_1_2;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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sPwm <= not sPwm after pwmPeriod/2;
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pwm <= sPwm;
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process
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constant testDelay: time := 10 us;
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begin
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motorOn <= '0';
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right_left <= '1';
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wait for testDelay;
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motorOn <= '1';
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wait for testDelay;
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right_left <= '0';
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wait for testDelay;
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motorOn <= '0';
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wait for testDelay;
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wait;
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end process;
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-- Instance port mappings.
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I_dut : ex_24_1_2
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PORT MAP (
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motorOn => motorOn,
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side1 => side1,
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right_left => right_left,
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pwm => pwm,
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side2 => side2
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);
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END struct;
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