2764 lines
34 KiB
Plaintext
2764 lines
34 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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instances [
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(Instance
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name "I_dut"
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duLibraryName "VHD"
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duName "ex_24_1_5"
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elements [
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(GiElement
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name "speedBitNb"
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type "positive"
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value "speedBitNb"
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)
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]
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mwi 0
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uid 1581,0
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)
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]
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embeddedInstances [
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(EmbeddedInstance
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name "eb1"
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number "1"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
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)
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(vvPair
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variable "appl"
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value "HDL Designer"
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)
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(vvPair
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variable "arch_name"
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value "struct"
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)
|
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(vvPair
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|
variable "concat_file"
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value "<TBD>"
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)
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(vvPair
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variable "config"
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value "%(unit)_config"
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)
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(vvPair
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variable "d"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5"
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)
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(vvPair
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variable "d_logical"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5"
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)
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(vvPair
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|
variable "date"
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value "20.03.2024"
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)
|
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(vvPair
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|
variable "day"
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|
value "mer."
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)
|
|
(vvPair
|
|
variable "day_long"
|
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value "mercredi"
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)
|
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(vvPair
|
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variable "dd"
|
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value "20"
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)
|
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(vvPair
|
|
variable "designName"
|
|
value "<TBD>"
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)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "tb_24_1_5"
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)
|
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(vvPair
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|
variable "ext"
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value "<TBD>"
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)
|
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(vvPair
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|
variable "f"
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|
value "struct.bd"
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)
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(vvPair
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variable "f_logical"
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value "struct.bd"
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)
|
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(vvPair
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variable "f_noext"
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value "struct"
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)
|
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(vvPair
|
|
variable "graphical_source_author"
|
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value "remy.borgeat"
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)
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(vvPair
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variable "graphical_source_date"
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value "20.03.2024"
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)
|
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(vvPair
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|
variable "graphical_source_group"
|
|
value "UNKNOWN"
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)
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(vvPair
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variable "graphical_source_host"
|
|
value "WE10993"
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)
|
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(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:01:25"
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|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
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)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE10993"
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)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
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|
)
|
|
(vvPair
|
|
variable "library"
|
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value "VHD_test"
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)
|
|
(vvPair
|
|
variable "library_downstream_HdsLintPlugin"
|
|
value "$HDS_PROJECT_DIR/../VHD_test/designcheck"
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|
)
|
|
(vvPair
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|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp"
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)
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(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Exam/VHD_test/work"
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|
)
|
|
(vvPair
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|
variable "mm"
|
|
value "03"
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|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "tb_24_1_5"
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|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "mars"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "mars"
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|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\struct.bd"
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)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\struct.bd"
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)
|
|
(vvPair
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|
variable "package_name"
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|
value "<Undefined Variable>"
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|
)
|
|
(vvPair
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|
variable "project_name"
|
|
value "hds"
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|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
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|
)
|
|
(vvPair
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|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
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|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
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|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "15:01:25"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "tb_24_1_5"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "remy.borgeat"
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)
|
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(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
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|
)
|
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(vvPair
|
|
variable "view"
|
|
value "struct"
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)
|
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(vvPair
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|
variable "year"
|
|
value "2024"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "24"
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|
)
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|
]
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)
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LanguageMgr "Vhdl2008LangMgr"
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uid 153,0
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|
|
xt "40000,50000,81000,55000"
|
|
)
|
|
oxt "14000,66000,55000,71000"
|
|
)
|
|
*12 (HdlText
|
|
uid 445,0
|
|
optionalChildren [
|
|
*13 (EmbeddedText
|
|
uid 450,0
|
|
commentText (CommentText
|
|
uid 451,0
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
uid 452,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "7000,24000,37000,34000"
|
|
)
|
|
oxt "0,0,18000,5000"
|
|
text (MLText
|
|
uid 453,0
|
|
va (VaSet
|
|
)
|
|
xt "7200,24200,30300,34200"
|
|
st "
|
|
reset <= '1', '0' after 2*clockPeriod;
|
|
sClock <= not sClock after clockPeriod/2;
|
|
clock <= transport sClock after clockPeriod*9/10;
|
|
|
|
process
|
|
constant testDelay: time := 2**(speedBitNb/2+3) * clockPeriod;
|
|
begin
|
|
start <= '0';
|
|
|
|
wait for testDelay;
|
|
start <= '1', '0' after clockPeriod;
|
|
|
|
wait for testDelay;
|
|
start <= '1', '0' after clockPeriod;
|
|
|
|
wait;
|
|
end process;
|
|
|
|
|
|
|
|
|
|
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 10000
|
|
visibleWidth 30000
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 446,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "6000,23000,38000,35000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
|
ttg (MlTextGroup
|
|
uid 447,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*14 (Text
|
|
uid 448,0
|
|
va (VaSet
|
|
)
|
|
xt "6400,35000,8000,36000"
|
|
st "eb1"
|
|
blo "6400,35800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*15 (Text
|
|
uid 449,0
|
|
va (VaSet
|
|
)
|
|
xt "6400,36000,7200,37000"
|
|
st "1"
|
|
blo "6400,36800"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
*16 (Net
|
|
uid 1122,0
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 11,0
|
|
)
|
|
declText (MLText
|
|
uid 1123,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,15800,12000,16800"
|
|
st "SIGNAL clock : std_ulogic"
|
|
)
|
|
)
|
|
*17 (Net
|
|
uid 1130,0
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 12,0
|
|
)
|
|
declText (MLText
|
|
uid 1131,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,17800,11900,18800"
|
|
st "SIGNAL reset : std_ulogic"
|
|
)
|
|
)
|
|
*18 (Net
|
|
uid 1498,0
|
|
decl (Decl
|
|
n "done"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 15,0
|
|
)
|
|
declText (MLText
|
|
uid 1499,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,16800,12000,17800"
|
|
st "SIGNAL done : std_ulogic"
|
|
)
|
|
)
|
|
*19 (Net
|
|
uid 1506,0
|
|
decl (Decl
|
|
n "speed"
|
|
t "unsigned"
|
|
b "(speedBitNb-1 downto 0)"
|
|
o 4
|
|
suid 16,0
|
|
)
|
|
declText (MLText
|
|
uid 1507,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,18800,20600,19800"
|
|
st "SIGNAL speed : unsigned(speedBitNb-1 downto 0)"
|
|
)
|
|
)
|
|
*20 (Net
|
|
uid 1514,0
|
|
decl (Decl
|
|
n "start"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 17,0
|
|
)
|
|
declText (MLText
|
|
uid 1515,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,19800,11700,20800"
|
|
st "SIGNAL start : std_ulogic"
|
|
)
|
|
)
|
|
*21 (SaComponent
|
|
uid 1581,0
|
|
optionalChildren [
|
|
*22 (CptPort
|
|
uid 1561,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1562,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,26625,46000,27375"
|
|
)
|
|
tg (CPTG
|
|
uid 1563,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1564,0
|
|
va (VaSet
|
|
font "Arial,9,0"
|
|
)
|
|
xt "47000,26550,49400,27750"
|
|
st "start"
|
|
blo "47000,27450"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "start"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 2004,0
|
|
)
|
|
)
|
|
)
|
|
*23 (CptPort
|
|
uid 1565,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1566,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,30625,46000,31375"
|
|
)
|
|
tg (CPTG
|
|
uid 1567,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1568,0
|
|
va (VaSet
|
|
font "Arial,9,0"
|
|
)
|
|
xt "47000,30550,49700,31750"
|
|
st "clock"
|
|
blo "47000,31450"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2005,0
|
|
)
|
|
)
|
|
)
|
|
*24 (CptPort
|
|
uid 1569,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1570,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,32625,46000,33375"
|
|
)
|
|
tg (CPTG
|
|
uid 1571,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1572,0
|
|
va (VaSet
|
|
font "Arial,9,0"
|
|
)
|
|
xt "47000,32550,49600,33750"
|
|
st "reset"
|
|
blo "47000,33450"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 2006,0
|
|
)
|
|
)
|
|
)
|
|
*25 (CptPort
|
|
uid 1573,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1574,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,28625,62750,29375"
|
|
)
|
|
tg (CPTG
|
|
uid 1575,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1576,0
|
|
va (VaSet
|
|
font "Arial,9,0"
|
|
)
|
|
xt "58500,28550,61000,29750"
|
|
st "done"
|
|
ju 2
|
|
blo "61000,29450"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "done"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 2008,0
|
|
)
|
|
)
|
|
)
|
|
*26 (CptPort
|
|
uid 1577,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1578,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,26625,62750,27375"
|
|
)
|
|
tg (CPTG
|
|
uid 1579,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1580,0
|
|
va (VaSet
|
|
font "Arial,9,0"
|
|
)
|
|
xt "58000,26550,61000,27750"
|
|
st "speed"
|
|
ju 2
|
|
blo "61000,27450"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "speed"
|
|
t "unsigned"
|
|
b "(speedBitNb-1 downto 0)"
|
|
o 5
|
|
suid 2009,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1582,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "46000,23000,62000,35000"
|
|
)
|
|
oxt "32000,12000,48000,24000"
|
|
ttg (MlTextGroup
|
|
uid 1583,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*27 (Text
|
|
uid 1584,0
|
|
va (VaSet
|
|
font "Arial,9,1"
|
|
)
|
|
xt "46600,34800,49100,35900"
|
|
st "VHD"
|
|
blo "46600,35700"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*28 (Text
|
|
uid 1585,0
|
|
va (VaSet
|
|
font "Arial,9,1"
|
|
)
|
|
xt "46600,35900,51600,37000"
|
|
st "ex_24_1_5"
|
|
blo "46600,36800"
|
|
tm "CptNameMgr"
|
|
)
|
|
*29 (Text
|
|
uid 1586,0
|
|
va (VaSet
|
|
font "Arial,9,1"
|
|
)
|
|
xt "46600,37000,49400,38100"
|
|
st "I_dut"
|
|
blo "46600,37900"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1587,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1588,0
|
|
text (MLText
|
|
uid 1589,0
|
|
va (VaSet
|
|
)
|
|
xt "46000,38400,61100,39400"
|
|
st "speedBitNb = speedBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "speedBitNb"
|
|
type "positive"
|
|
value "speedBitNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
connectByName 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*30 (Wire
|
|
uid 1124,0
|
|
shape (OrthoPolyLine
|
|
uid 1125,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "38000,31000,45250,31000"
|
|
pts [
|
|
"45250,31000"
|
|
"38000,31000"
|
|
]
|
|
)
|
|
start &23
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1128,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1129,0
|
|
va (VaSet
|
|
font "Arial,12,0"
|
|
)
|
|
xt "40250,29700,43750,31200"
|
|
st "clock"
|
|
blo "40250,30900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*31 (Wire
|
|
uid 1132,0
|
|
shape (OrthoPolyLine
|
|
uid 1133,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "38000,33000,45250,33000"
|
|
pts [
|
|
"45250,33000"
|
|
"38000,33000"
|
|
]
|
|
)
|
|
start &24
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1136,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1137,0
|
|
va (VaSet
|
|
font "Arial,12,0"
|
|
)
|
|
xt "40250,31700,43750,33200"
|
|
st "reset"
|
|
blo "40250,32900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*32 (Wire
|
|
uid 1500,0
|
|
shape (OrthoPolyLine
|
|
uid 1501,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "62750,29000,70000,29000"
|
|
pts [
|
|
"62750,29000"
|
|
"70000,29000"
|
|
]
|
|
)
|
|
start &25
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1504,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1505,0
|
|
va (VaSet
|
|
font "Arial,12,0"
|
|
)
|
|
xt "64750,27700,68250,29200"
|
|
st "done"
|
|
blo "64750,28900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &18
|
|
)
|
|
*33 (Wire
|
|
uid 1508,0
|
|
shape (OrthoPolyLine
|
|
uid 1509,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "62750,27000,70000,27000"
|
|
pts [
|
|
"62750,27000"
|
|
"70000,27000"
|
|
]
|
|
)
|
|
start &26
|
|
sat 32
|
|
eat 16
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1512,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1513,0
|
|
va (VaSet
|
|
font "Arial,12,0"
|
|
)
|
|
xt "64750,25700,68950,27200"
|
|
st "speed"
|
|
blo "64750,26900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*34 (Wire
|
|
uid 1516,0
|
|
shape (OrthoPolyLine
|
|
uid 1517,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "38000,27000,45250,27000"
|
|
pts [
|
|
"45250,27000"
|
|
"38000,27000"
|
|
]
|
|
)
|
|
start &22
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1520,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1521,0
|
|
va (VaSet
|
|
font "Arial,12,0"
|
|
)
|
|
xt "40250,25700,43350,27200"
|
|
st "start"
|
|
blo "40250,26900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &20
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 1
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *35 (PackageList
|
|
uid 142,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*36 (Text
|
|
uid 143,0
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optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Arial,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Arial,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Arial,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Arial,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1000,2000"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,3100,1000"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,6300,2000"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,12500,-100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*62 (Text
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*63 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,7300,-100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*64 (Text
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*65 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "0,4800,5400,5800"
|
|
st "Declarations"
|
|
blo "0,5600"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "0,5800,2700,6800"
|
|
st "Ports:"
|
|
blo "0,6600"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "0,6800,3800,7800"
|
|
st "Pre User:"
|
|
blo "0,7600"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,7800,23700,14800"
|
|
st "constant speedBitNb : positive := 8;
|
|
|
|
constant clockFrequency : real := 100.0E6;
|
|
constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
|
|
signal sClock : std_uLogic := '1';
|
|
|
|
signal position_int : integer := 0;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "0,14800,7100,15800"
|
|
st "Diagram Signals:"
|
|
blo "0,15600"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Arial,8,1"
|
|
)
|
|
xt "0,4800,4700,5800"
|
|
st "Post User:"
|
|
blo "0,5600"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "0,4800,0,4800"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 17,0
|
|
usingSuid 1
|
|
emptyRow *66 (LEmptyRow
|
|
)
|
|
uid 565,0
|
|
optionalChildren [
|
|
*67 (RefLabelRowHdr
|
|
)
|
|
*68 (TitleRowHdr
|
|
)
|
|
*69 (FilterRowHdr
|
|
)
|
|
*70 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*71 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*72 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*73 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*74 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*75 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*76 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*77 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*78 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*79 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 11,0
|
|
)
|
|
)
|
|
uid 1144,0
|
|
)
|
|
*80 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 12,0
|
|
)
|
|
)
|
|
uid 1146,0
|
|
)
|
|
*81 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "done"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 15,0
|
|
)
|
|
)
|
|
uid 1522,0
|
|
)
|
|
*82 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "speed"
|
|
t "unsigned"
|
|
b "(speedBitNb-1 downto 0)"
|
|
o 4
|
|
suid 16,0
|
|
)
|
|
)
|
|
uid 1524,0
|
|
)
|
|
*83 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "start"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 17,0
|
|
)
|
|
)
|
|
uid 1526,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 578,0
|
|
optionalChildren [
|
|
*84 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *85 (MRCItem
|
|
litem &66
|
|
pos 5
|
|
dimension 20
|
|
)
|
|
uid 580,0
|
|
optionalChildren [
|
|
*86 (MRCItem
|
|
litem &67
|
|
pos 0
|
|
dimension 20
|
|
uid 581,0
|
|
)
|
|
*87 (MRCItem
|
|
litem &68
|
|
pos 1
|
|
dimension 23
|
|
uid 582,0
|
|
)
|
|
*88 (MRCItem
|
|
litem &69
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 583,0
|
|
)
|
|
*89 (MRCItem
|
|
litem &79
|
|
pos 0
|
|
dimension 20
|
|
uid 1145,0
|
|
)
|
|
*90 (MRCItem
|
|
litem &80
|
|
pos 1
|
|
dimension 20
|
|
uid 1147,0
|
|
)
|
|
*91 (MRCItem
|
|
litem &81
|
|
pos 2
|
|
dimension 20
|
|
uid 1523,0
|
|
)
|
|
*92 (MRCItem
|
|
litem &82
|
|
pos 3
|
|
dimension 20
|
|
uid 1525,0
|
|
)
|
|
*93 (MRCItem
|
|
litem &83
|
|
pos 4
|
|
dimension 20
|
|
uid 1527,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 584,0
|
|
optionalChildren [
|
|
*94 (MRCItem
|
|
litem &70
|
|
pos 0
|
|
dimension 20
|
|
uid 585,0
|
|
)
|
|
*95 (MRCItem
|
|
litem &72
|
|
pos 1
|
|
dimension 50
|
|
uid 586,0
|
|
)
|
|
*96 (MRCItem
|
|
litem &73
|
|
pos 2
|
|
dimension 100
|
|
uid 587,0
|
|
)
|
|
*97 (MRCItem
|
|
litem &74
|
|
pos 3
|
|
dimension 50
|
|
uid 588,0
|
|
)
|
|
*98 (MRCItem
|
|
litem &75
|
|
pos 4
|
|
dimension 100
|
|
uid 589,0
|
|
)
|
|
*99 (MRCItem
|
|
litem &76
|
|
pos 5
|
|
dimension 100
|
|
uid 590,0
|
|
)
|
|
*100 (MRCItem
|
|
litem &77
|
|
pos 6
|
|
dimension 50
|
|
uid 591,0
|
|
)
|
|
*101 (MRCItem
|
|
litem &78
|
|
pos 7
|
|
dimension 80
|
|
uid 592,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 579,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 564,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *102 (LEmptyRow
|
|
)
|
|
uid 594,0
|
|
optionalChildren [
|
|
*103 (RefLabelRowHdr
|
|
)
|
|
*104 (TitleRowHdr
|
|
)
|
|
*105 (FilterRowHdr
|
|
)
|
|
*106 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*107 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*108 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*109 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*110 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*111 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*112 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*113 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 606,0
|
|
optionalChildren [
|
|
*114 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *115 (MRCItem
|
|
litem &102
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 608,0
|
|
optionalChildren [
|
|
*116 (MRCItem
|
|
litem &103
|
|
pos 0
|
|
dimension 20
|
|
uid 609,0
|
|
)
|
|
*117 (MRCItem
|
|
litem &104
|
|
pos 1
|
|
dimension 23
|
|
uid 610,0
|
|
)
|
|
*118 (MRCItem
|
|
litem &105
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 611,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 612,0
|
|
optionalChildren [
|
|
*119 (MRCItem
|
|
litem &106
|
|
pos 0
|
|
dimension 20
|
|
uid 613,0
|
|
)
|
|
*120 (MRCItem
|
|
litem &108
|
|
pos 1
|
|
dimension 50
|
|
uid 614,0
|
|
)
|
|
*121 (MRCItem
|
|
litem &109
|
|
pos 2
|
|
dimension 100
|
|
uid 615,0
|
|
)
|
|
*122 (MRCItem
|
|
litem &110
|
|
pos 3
|
|
dimension 100
|
|
uid 616,0
|
|
)
|
|
*123 (MRCItem
|
|
litem &111
|
|
pos 4
|
|
dimension 50
|
|
uid 617,0
|
|
)
|
|
*124 (MRCItem
|
|
litem &112
|
|
pos 5
|
|
dimension 50
|
|
uid 618,0
|
|
)
|
|
*125 (MRCItem
|
|
litem &113
|
|
pos 6
|
|
dimension 80
|
|
uid 619,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 607,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 593,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|