exercice 5

VHD/hdl/ex_24_1_5_studentVersion.vhd

@@ -1,5 +1,52 @@
 architecture studentVersion of ex_24_1_5 is
+
+  signal running : std_ulogic;
+  signal deccel : std_ulogic;
+  signal counter : unsigned(speedBitNb/2-1 downto 0);
+  signal accumulator : unsigned(speedBitNb-1 downto 0);
+
 begin
-  speed <= (others => '0');
-  done <= '0';
+  process(clock, reset) begin
+    if reset = '1' then
+
+      running <= '0';
+      deccel <= '0';
+      counter <= (others => '0');
+      accumulator <= (others => '0');
+      speed <= (others => '0');
+      done <= '0';
+    
+    elsif rising_edge(clock) then 
+      
+      if start = '1' then
+        running <= '1';
+        deccel <= '0';
+        counter <= (others => '0');
+        accumulator <= (others => '0'); -- Comment this line if you want 2 accel without overflow (l.38-39)
+      end if;
+
+      if running = '1' then
+        if deccel = '0' then
+          counter <= counter + 1;
+        else
+          counter <= counter - 1;
+        end if;
+        accumulator <= accumulator + counter;
+        speed <= accumulator;    
+      end if;
+
+      --if ((counter = 2**(speedBitNb/2-1)) and (deccel = '0')) then -- For 2 accel without overflow
+      if ((counter = 2**((speedBitNb/2))-2) and (deccel = '0')) then -- For best fit for only one acceleration
+        deccel <= '1';
+        done <= '1';
+      else
+        done <= '0';
+      end if;
+
+      if ((deccel = '1') and (counter = 0)) then
+        running <= '0';
+      end if;
+
+    end if;
+  end process;
 end studentVersion;