exercice 5

VHD/hdl/ex_24_1_5_entity.vhd

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+-- VHDL Entity VHD.ex_24_1_5.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:07:26 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_24_1_5 IS
+   GENERIC( 
+      speedBitNb : positive
+   );
+   PORT( 
+      start : IN     std_ulogic;
+      clock : IN     std_ulogic;
+      reset : IN     std_ulogic;
+      done  : OUT    std_ulogic;
+      speed : OUT    unsigned (speedBitNb-1 DOWNTO 0)
+   );
+
+-- Declarations
+
+END ex_24_1_5 ;
+