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VHD/hdl/ex_24_1_1_entity.vhd

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+-- VHDL Entity VHD.ex_24_1_1.symbol
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:02:45 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_24_1_1 IS
+   GENERIC( 
+      counterBitNb : positive := 8
+   );
+   PORT( 
+      en       : IN     std_ulogic;
+      position : OUT    unsigned (counterBitNb-1 DOWNTO 0);
+      up_down  : IN     std_ulogic;
+      clock    : IN     std_ulogic;
+      reset    : IN     std_ulogic
+   );
+
+-- Declarations
+
+END ex_24_1_1 ;
+