Klagarge/SEm-ExamMidterm2024
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Rémi Heredero
2024-03-22 13:16:48 +01:00
commit 8b2f630f7b
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20
Prefs/hds_user-linux/v2016.1/templates/registered_views/Vunit_VHDL.psl Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name).psl
DESCRIPTION_START
This is the default template used for the creation of PSL Vunit (VHDL) files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- PSL Vunit(VHDL Syntax)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
vunit %(view) (%(unit))
{
default clock IS ClockName;
}

20
Prefs/hds_user-linux/v2016.1/templates/registered_views/Vunit_Verilog.psl Normal file
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FILE_NAMING_RULE: %(unit).psl
DESCRIPTION_START
This is the default template used for the creation of PSL Vunit (Verilog) files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// PSL Vunit(Verilog Syntax)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
vunit %(view) (%(unit))
{
default clock = ClockName;
}

13
Prefs/hds_user-linux/v2016.1/templates/registered_views/c_file.c Normal file
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FILE_NAMING_RULE: c_file.c
DESCRIPTION_START
This is the default template used for the creation of C files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
/*
* Created:
* by - %(user).%(group) (%(host))
* at - %(time) %(date)
*
* using Mentor Graphics HDL Designer(TM) %(version)
*/

12
Prefs/hds_user-linux/v2016.1/templates/registered_views/class.cpp Normal file
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FILE_NAMING_RULE: afile.cpp
DESCRIPTION_START
This is the default template used for the creation of C++ files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//

18
Prefs/hds_user-linux/v2016.1/templates/verilog_Class/class.svh Normal file
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FILE_NAMING_RULE: %(class_name).svh
DESCRIPTION_START
This is the default template used for the creation of Class files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Verilog class %(library).%(unit)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
%(classBody)
// ### Please start your Verilog code here ###
endclass

18
Prefs/hds_user-linux/v2016.1/templates/verilog_Interface/interface.sv Normal file
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FILE_NAMING_RULE: %(interface_name).sv
DESCRIPTION_START
This is the default template used for the creation of Interface files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Verilog interface %(library).%(unit)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
%(interfaceBody)
// ### Please start your Verilog code here ###
endinterface

18
Prefs/hds_user-linux/v2016.1/templates/verilog_Package/package.sv Normal file
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FILE_NAMING_RULE: %(package_name).sv
DESCRIPTION_START
This is the default template used for the creation of Package files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Verilog package %(library).%(unit)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
%(packageBody)
// ### Please start your Verilog code here ###
endpackage

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Prefs/hds_user-linux/v2016.1/templates/verilog_Program/program.sv Normal file
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FILE_NAMING_RULE: %(program_name).sv
DESCRIPTION_START
This is the default template used for the creation of program files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Verilog program %(library).%(unit)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
%(programBody)
// ### Please start your Verilog code here ###
endprogram

14
Prefs/hds_user-linux/v2016.1/templates/verilog_include/verilog_include.v Normal file
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FILE_NAMING_RULE: include_filename.v
DESCRIPTION_START
This is the default template used for the creation of Verilog Include files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Include file %(library)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//

18
Prefs/hds_user-linux/v2016.1/templates/verilog_module/module.v Normal file
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FILE_NAMING_RULE: %(module_name).v
DESCRIPTION_START
This is the default template used for the creation of Verilog Module files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Verilog Module %(library).%(unit)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
%(moduleBody)
// ### Please start your Verilog code here ###
endmodule

15
Prefs/hds_user-linux/v2016.1/templates/vhdl_architecture/architecture.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
Prefs/hds_user-linux/v2016.1/templates/vhdl_combined/combined.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
Prefs/hds_user-linux/v2016.1/templates/vhdl_configuration/configuration.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
Prefs/hds_user-linux/v2016.1/templates/vhdl_entity/entity.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
Prefs/hds_user-linux/v2016.1/templates/vhdl_package_body/package_body.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
Prefs/hds_user-linux/v2016.1/templates/vhdl_package_header/package_header.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);