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Prefs/hds_user-linux/v2015.2/templates/verilog_include/verilog_include.v

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+FILE_NAMING_RULE: include_filename.v
+DESCRIPTION_START
+This is the default template used for the creation of Verilog Include files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Include file %(library)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//