Initial commit

2024-03-22 13:16:48 +01:00
commit 8b2f630f7b
499 changed files with 87136 additions and 0 deletions
--- a/Prefs/hds_user/v2009.2/hds_user_prefs
+++ b/Prefs/hds_user/v2009.2/hds_user_prefs
--- a/Prefs/hds_user/v2009.2/tasks/concatenate_hdl.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/concatenate_hdl.tsk
@@ -0,0 +1,54 @@
+version "1.1"
+HDSTool (HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "Concatenate HDL"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp"
+hasBitmap 1
+tooltip "Appends all HDL files together"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+""
+"captureOutput"
+"1"
+"customPrompt"
+""
+"initialDir"
+""
+"promptForRunSettings"
+"0"
+"runnableObject"
+"Concatenation"
+"runnableObjectType"
+"tcl_plugin"
+"useViewSpecific"
+"1"
+]
+)
+"TaskSetting"
+(SettingsMap
+settingsMap [
+"outputFileNameRoot"
+"%(concat_file)"
+"outputVerilogFileExtension"
+"v"
+"outputVhdlFileExtension"
+"vhd"
+"place"
+"0"
+"specifyDir"
+""
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+)
--- a/Prefs/hds_user/v2009.2/tasks/designchecker.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/designchecker.tsk
@@ -0,0 +1,46 @@
+version "1.1"
+HDSTool (HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "DesignChecker"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp"
+hasBitmap 1
+tooltip "Runs DesignChecker"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+""
+"captureOutput"
+"1"
+"customPrompt"
+""
+"initialDir"
+""
+"promptForRunSettings"
+"0"
+"runnableObject"
+"HdsLintPlugin"
+"runnableObjectType"
+"tcl_plugin"
+"useViewSpecific"
+"0"
+]
+)
+"TaskSetting"
+(SettingsMap
+settingsMap [
+"Policy"
+"My_Essentials_Policy"
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+)
--- a/Prefs/hds_user/v2009.2/tasks/designchecker_flow.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/designchecker_flow.tsk
@@ -0,0 +1,57 @@
+version "1.1"
+HDSFlow (HDSFlow
+TaskName "DesignChecker Flow"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp"
+hasBitmap 1
+tooltip "Generate and runs DesignChecker"
+taskSettings [
+]
+PreferedTasks [
+]
+onShortcutBar 1
+onPulldownMenu 1
+onToolbar 1
+enabled 1
+hierDepth 1
+subTasks [
+(HDSTaskRef
+TaskName "Generate"
+bitmap ""
+hasBitmap 1
+tooltip ""
+taskSettings [
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+reffedTaskName "USER:Generate"
+)
+(HDSTaskRef
+TaskName "DesignChecker"
+bitmap ""
+hasBitmap 1
+tooltip ""
+taskSettings [
+"TaskSetting"
+(SettingsMap
+settingsMap [
+"Policy"
+"My_Essentials_Policy"
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+reffedTaskName "USER:DesignChecker"
+)
+]
+)
--- a/Prefs/hds_user/v2009.2/tasks/generate.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/generate.tsk
@@ -0,0 +1,46 @@
+version "1.1"
+HDSTool (HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "Generate"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
+hasBitmap 1
+tooltip "Performs generation of graphics files"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+""
+"captureOutput"
+"0"
+"customPrompt"
+""
+"initialDir"
+""
+"promptForRunSettings"
+"0"
+"runnableObject"
+"Generator"
+"runnableObjectType"
+"tcl_plugin"
+"useViewSpecific"
+"0"
+]
+)
+"TaskSetting"
+(SettingsMap
+settingsMap [
+"generateAlways"
+"0"
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 1
+onPulldownMenu 1
+onToolbar 1
+enabled 1
+hierDepth 1
+)
--- a/Prefs/hds_user/v2009.2/tasks/modelsim_compile.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/modelsim_compile.tsk
@@ -0,0 +1,48 @@
+version "1.1"
+HDSTool (HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "ModelSim Compile"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp"
+hasBitmap 1
+tooltip "Runs ModelSim compilation"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+""
+"captureOutput"
+"0"
+"customPrompt"
+""
+"initialDir"
+""
+"promptForRunSettings"
+"0"
+"runnableObject"
+"ModelSimCompiler"
+"runnableObjectType"
+"tcl_plugin"
+"useViewSpecific"
+"0"
+]
+)
+"TaskSetting"
+(SettingsMap
+settingsMap [
+"exepath"
+"%task_ModelSimPath"
+"peSe"
+"EE"
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+)
--- a/Prefs/hds_user/v2009.2/tasks/modelsim_flow.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/modelsim_flow.tsk
@@ -0,0 +1,74 @@
+version "1.1"
+HDSFlow (HDSFlow
+TaskName "ModelSim Flow"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp"
+hasBitmap 1
+tooltip "Generate and run entire ModelSim flow"
+taskSettings [
+]
+PreferedTasks [
+(preferedMap
+preferedEnum 0
+preferedSetting "C:\\EDA\\Modelsim\\win32"
+)
+(preferedMap
+preferedEnum 2
+preferedSetting "ModelSim SE 6.3g"
+)
+]
+onShortcutBar 1
+onPulldownMenu 1
+onToolbar 1
+enabled 1
+hierDepth 1
+subTasks [
+(HDSTaskRef
+TaskName "Generate"
+bitmap ""
+hasBitmap 1
+tooltip ""
+taskSettings [
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+reffedTaskName "USER:Generate"
+)
+(HDSTaskRef
+TaskName "ModelSim Compile"
+bitmap ""
+hasBitmap 1
+tooltip ""
+taskSettings [
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+reffedTaskName "USER:ModelSim Compile"
+)
+(HDSTaskRef
+TaskName "ModelSim Simulate"
+bitmap ""
+hasBitmap 1
+tooltip ""
+taskSettings [
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 3
+reffedTaskName "USER:ModelSim Simulate"
+)
+]
+)
--- a/Prefs/hds_user/v2009.2/tasks/modelsim_simulate.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/modelsim_simulate.tsk
@@ -0,0 +1,86 @@
+version "1.1"
+HDSTool (HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "ModelSim Simulate"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
+hasBitmap 1
+tooltip "Invokes the ModelSim Simulator"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+""
+"captureOutput"
+"0"
+"customPrompt"
+""
+"initialDir"
+""
+"promptForRunSettings"
+"1"
+"runnableObject"
+"ModelSimSimulator"
+"runnableObjectType"
+"tcl_plugin"
+"useViewSpecific"
+"0"
+]
+)
+"TaskSetting"
+(SettingsMap
+settingsMap [
+"Arguments"
+""
+"Communication"
+"1"
+"DelaySelection"
+"typ"
+"GlitchGeneration"
+"1"
+"InitCmd"
+"$SIMULATION_DIR/wave_15_2_1.do"
+"LogFile"
+""
+"RemoteHost"
+""
+"Resolution"
+"fs"
+"SdfDelay"
+"typ"
+"SdfMultiSrcDelay"
+"latest"
+"SdfReduce"
+"0"
+"SdfWarnings"
+"1"
+"TimingChecks"
+"1"
+"UseBatch"
+"0"
+"UseGUI"
+"1"
+"VitalVersion"
+"95"
+"Simulate"
+"1"
+"excludePSL"
+"0"
+"exepath"
+"%task_ModelSimPath"
+"saveReplayScript"
+"0"
+"useCustomSimDir"
+"0"
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 3
+)
--- a/Prefs/hds_user/v2009.2/tasks/synthesis_flow.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/synthesis_flow.tsk
@@ -0,0 +1,134 @@
+version "1.1"
+HDSFlow (HDSFlow
+TaskName "Synthesis Flow"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_leonardo.bmp"
+hasBitmap 1
+tooltip "Single file VHDL Synthesis Flow"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"flowSettingsDlg"
+""
+"taskInvocationScript"
+""
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+subTasks [
+(HDSTaskRef
+TaskName "Generate"
+bitmap ""
+hasBitmap 1
+tooltip ""
+taskSettings [
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+reffedTaskName "USER:Generate"
+)
+(HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "Concatenate HDL"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp"
+hasBitmap 1
+tooltip "Appends all HDL files together"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+""
+"captureOutput"
+"1"
+"customPrompt"
+""
+"initialDir"
+""
+"promptForRunSettings"
+"0"
+"runnableObject"
+"Concatenation"
+"runnableObjectType"
+"tcl_plugin"
+"useViewSpecific"
+"1"
+]
+)
+"TaskSetting"
+(SettingsMap
+settingsMap [
+"outputFileNameRoot"
+"%(concat_file)"
+"outputVerilogFileExtension"
+"v"
+"outputVhdlFileExtension"
+"vhd"
+"place"
+"0"
+"specifyDir"
+""
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 1
+)
+(HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "Trim libs"
+bitmap "tool_default_tool.bmp"
+hasBitmap 1
+tooltip "Comment out library declarations for single file VHDL"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+"trimlibs.pl %(concat_file).vhd"
+"captureOutput"
+"1"
+"customPrompt"
+""
+"initialDir"
+"%(library_downstream_Concatenation)"
+"promptForRunSettings"
+"0"
+"runnableObject"
+"%(task_HDSPath)\\resources\\perl\\bin\\perl.exe"
+"runnableObjectType"
+"executable"
+"useViewSpecific"
+"0"
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 3
+)
+]
+)
--- a/Prefs/hds_user/v2009.2/tasks/trim_libraries.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/trim_libraries.tsk
@@ -0,0 +1,39 @@
+version "1.1"
+HDSTool (HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "Trim libraries"
+bitmap "tool_default_tool.bmp"
+hasBitmap 1
+tooltip "Comment out library declarations for single file VHDL"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+"trimlibs.pl %(concat_file).vhd"
+"captureOutput"
+"1"
+"customPrompt"
+""
+"initialDir"
+"%(library_downstream_Concatenation)"
+"promptForRunSettings"
+"0"
+"runnableObject"
+"C:\\eda\\hds\\resources\\perl\\bin\\perl.exe"
+"runnableObjectType"
+"executable"
+"useViewSpecific"
+"0"
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 3
+)
--- a/Prefs/hds_user/v2009.2/tasks/xilinx_project_navigator.tsk
+++ b/Prefs/hds_user/v2009.2/tasks/xilinx_project_navigator.tsk
@@ -0,0 +1,39 @@
+version "1.1"
+HDSTool (HDSTool
+hasAssociatedFileExt 0
+associatedFileExt ""
+TaskName "Xilinx Project Navigator"
+bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_projnav.bmp"
+hasBitmap 1
+tooltip "Invokes the Xilinx ISE tool"
+taskSettings [
+"InternalTaskSetting"
+(SettingsMap
+settingsMap [
+"additionalToolArgs"
+"%(designName).xise"
+"captureOutput"
+"0"
+"customPrompt"
+""
+"initialDir"
+"%(task_ISEPath)"
+"promptForRunSettings"
+"0"
+"runnableObject"
+"%(task_ISEBinPath)\\ISE\\bin\\nt\\ise.exe"
+"runnableObjectType"
+"executable"
+"useViewSpecific"
+"0"
+]
+)
+]
+PreferedTasks [
+]
+onShortcutBar 0
+onPulldownMenu 0
+onToolbar 0
+enabled 1
+hierDepth 3
+)
--- a/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_VHDL.psl
+++ b/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_VHDL.psl
@@ -0,0 +1,19 @@
+DESCRIPTION_START
+This is the default template used for the creation of PSL Vunit (VHDL) files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- PSL Vunit(VHDL Syntax)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+
+vunit %(view) ([%(unit)])
+{
+    default clock IS ClockName;
+    
+}
--- a/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_Verilog.psl
+++ b/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_Verilog.psl
@@ -0,0 +1,19 @@
+DESCRIPTION_START
+This is the default template used for the creation of PSL Vunit (Verilog) files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// PSL Vunit(Verilog Syntax)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+
+vunit %(view) ([%(unit)])
+{
+    default clock = ClockName;
+    
+}
--- a/Prefs/hds_user/v2009.2/templates/registered_views/c_file.c
+++ b/Prefs/hds_user/v2009.2/templates/registered_views/c_file.c
@@ -0,0 +1,13 @@
+FILE_NAMING_RULE: c_file.c
+DESCRIPTION_START
+This is the default template used for the creation of C files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+/*
+ * Created:
+ *         by - %(user).%(group) (%(host))
+ *         at - %(time) %(date)
+ *
+ * using Mentor Graphics HDL Designer(TM) %(version)
+ */
+
--- a/Prefs/hds_user/v2009.2/templates/registered_views/sc_source.cpp
+++ b/Prefs/hds_user/v2009.2/templates/registered_views/sc_source.cpp
@@ -0,0 +1,59 @@
+FILE_NAMING_RULE: %(unit).cpp
+DESCRIPTION_START
+This is the default template used for the creation of SystemC source files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+// Filename: %(view)
+
+#include "systemc.h"
+//#include "%(unit).h"
+
+// Method body for %(unit)_action
+void %(unit)::%(unit)_action()
+{
+
+}
+
+SC_MODULE_EXPORT(%(unit));
+
+//
+// It is recommended that the SC_MODULE code is placed in a separate header file
+// If required, you can copy/paste the following template code into a header file
+// called %(unit).h and uncomment the #include statement above.
+
+//#ifndef %(unit)_H
+//#define %(unit)_H
+//
+//#include "systemc.h"
+//
+//SC_MODULE (%(unit))
+//{
+//  // Ports
+//  sc_in<bool> clk,
+//  sc_in<int>  in2;
+//  sc_out<int> out1;
+//
+//  // Methods
+//  void %(unit)_action();
+//
+//  // %(unit) Constructor
+//  SC_CTOR(%(unit))
+//	  :
+//  {
+//    SC_THREAD(%(unit)_action);
+//    sensitive << clk.pos();
+//  }
+//
+//  // %(unit) Destructor
+//  ~%(unit)
+//  {
+//  }
+//
+//};
--- a/Prefs/hds_user/v2009.2/templates/verilog_Class/class.svh
+++ b/Prefs/hds_user/v2009.2/templates/verilog_Class/class.svh
@@ -0,0 +1,18 @@
+FILE_NAMING_RULE: %(class_name).svh
+DESCRIPTION_START
+This is the default template used for the creation of Class files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Verilog class %(library).%(unit)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+%(classBody)
+// ### Please start your Verilog code here ### 
+
+endclass
--- a/Prefs/hds_user/v2009.2/templates/verilog_Interface/interface.sv
+++ b/Prefs/hds_user/v2009.2/templates/verilog_Interface/interface.sv
@@ -0,0 +1,18 @@
+FILE_NAMING_RULE: %(interface_name).sv
+DESCRIPTION_START
+This is the default template used for the creation of Interface files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Verilog interface %(library).%(unit)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+%(interfaceBody)
+
+// ### Please start your Verilog code here ### 
+endinterface
--- a/Prefs/hds_user/v2009.2/templates/verilog_Package/package.sv
+++ b/Prefs/hds_user/v2009.2/templates/verilog_Package/package.sv
@@ -0,0 +1,18 @@
+FILE_NAMING_RULE: %(package_name).sv
+DESCRIPTION_START
+This is the default template used for the creation of Package files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Verilog package %(library).%(unit)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+%(packageBody)
+// ### Please start your Verilog code here ### 
+
+endpackage
--- a/Prefs/hds_user/v2009.2/templates/verilog_Program/program.sv
+++ b/Prefs/hds_user/v2009.2/templates/verilog_Program/program.sv
@@ -0,0 +1,18 @@
+FILE_NAMING_RULE: %(program_name).sv
+DESCRIPTION_START
+This is the default template used for the creation of program files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Verilog program %(library).%(unit)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+%(programBody)
+
+// ### Please start your Verilog code here ### 
+endprogram
--- a/Prefs/hds_user/v2009.2/templates/verilog_include/verilog_include.v
+++ b/Prefs/hds_user/v2009.2/templates/verilog_include/verilog_include.v
@@ -0,0 +1,14 @@
+FILE_NAMING_RULE: include_filename.v
+DESCRIPTION_START
+This is the default template used for the creation of Verilog Include files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Include file %(library)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
--- a/Prefs/hds_user/v2009.2/templates/verilog_module/module.v
+++ b/Prefs/hds_user/v2009.2/templates/verilog_module/module.v
@@ -0,0 +1,18 @@
+FILE_NAMING_RULE: %(module_name).v
+DESCRIPTION_START
+This is the default template used for the creation of Verilog Module files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Verilog Module %(library).%(unit)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+%(moduleBody)
+// ### Please start your Verilog code here ### 
+
+endmodule
--- a/Prefs/hds_user/v2009.2/templates/verilog_module/module_migrated.v
+++ b/Prefs/hds_user/v2009.2/templates/verilog_module/module_migrated.v
@@ -0,0 +1,22 @@
+FILE_NAMING_RULE: %(module_name).v
+DESCRIPTION_START
+Template for the creation of Verilog Module files.
+This template was migrated from header preferences created in a
+previous version of HDL Designer.
+DESCRIPTION_END
+// 
+//
+// Module %(library).%(unit).%(view)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// Generated by Mentor Graphics' HDL Designer(TM) %(version)
+//
+// 
+%(moduleBody)
+// 
+// ### Please start your Verilog code here ### 
+
+endmodule
--- a/Prefs/hds_user/v2009.2/templates/vhdl_architecture/architecture.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_architecture/architecture.vhd
@@ -0,0 +1,15 @@
+FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Architecture files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Architecture %(library).%(unit).%(view)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+%(architecture)
--- a/Prefs/hds_user/v2009.2/templates/vhdl_architecture_old/architecture.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_architecture_old/architecture.vhd
@@ -0,0 +1,15 @@
+FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Architecture files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Architecture %(library).%(unit).%(view)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+%(architecture)
--- a/Prefs/hds_user/v2009.2/templates/vhdl_combined/combined.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_combined/combined.vhd
@@ -0,0 +1,17 @@
+FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
+DESCRIPTION_START
+This is the default template used for the creation of combined VHDL Architecture and Entity files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Architecture %(library).%(unit).%(view)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+%(entity)
+--
+%(architecture)
--- a/Prefs/hds_user/v2009.2/templates/vhdl_combined_old/combined.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_combined_old/combined.vhd
@@ -0,0 +1,17 @@
+FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
+DESCRIPTION_START
+This is the default template used for the creation of combined VHDL Architecture and Entity files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Architecture %(library).%(unit).%(view)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+%(entity)
+--
+%(architecture)
--- a/Prefs/hds_user/v2009.2/templates/vhdl_configuration/configuration.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_configuration/configuration.vhd
@@ -0,0 +1,19 @@
+FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Configuration files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Configuration %(library).%(unit).%(view)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+CONFIGURATION %(entity_name)_config OF %(entity_name) IS
+   FOR %(arch_name)
+   END FOR;
+END %(entity_name)_config;
+
--- a/Prefs/hds_user/v2009.2/templates/vhdl_configuration_old/configuration.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_configuration_old/configuration.vhd
@@ -0,0 +1,19 @@
+FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Configuration files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Configuration %(library).%(unit).%(view)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+CONFIGURATION %(entity_name)_config OF %(entity_name) IS
+   FOR %(arch_name)
+   END FOR;
+END %(entity_name)_config;
+
--- a/Prefs/hds_user/v2009.2/templates/vhdl_entity/entity.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_entity/entity.vhd
@@ -0,0 +1,15 @@
+FILE_NAMING_RULE: %(entity_name)_entity.vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Entity files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Entity %(library).%(unit).%(view)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+%(entity)
--- a/Prefs/hds_user/v2009.2/templates/vhdl_entity_old/entity.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_entity_old/entity.vhd
@@ -0,0 +1,15 @@
+FILE_NAMING_RULE: %(entity_name)_entity.vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Entity files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Entity %(library).%(unit).%(view)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+%(entity)
--- a/Prefs/hds_user/v2009.2/templates/vhdl_package_body/package_body.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_package_body/package_body.vhd
@@ -0,0 +1,16 @@
+FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Package Body files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Package Body %(library).%(unit)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+PACKAGE BODY %(entity_name) IS
+END %(entity_name);
--- a/Prefs/hds_user/v2009.2/templates/vhdl_package_body_old/package_body.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_package_body_old/package_body.vhd
@@ -0,0 +1,16 @@
+FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Package Body files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Package Body %(library).%(unit)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+PACKAGE BODY %(entity_name) IS
+END %(entity_name);
--- a/Prefs/hds_user/v2009.2/templates/vhdl_package_header/package_header.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_package_header/package_header.vhd
@@ -0,0 +1,18 @@
+FILE_NAMING_RULE: %(entity_name)_pkg.vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Package Header files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Package Header %(library).%(unit)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+PACKAGE %(entity_name) IS
+END %(entity_name);
--- a/Prefs/hds_user/v2009.2/templates/vhdl_package_headerù_old/package_header.vhd
+++ b/Prefs/hds_user/v2009.2/templates/vhdl_package_headerù_old/package_header.vhd
@@ -0,0 +1,18 @@
+FILE_NAMING_RULE: %(entity_name)_pkg.vhd
+DESCRIPTION_START
+This is the default template used for the creation of VHDL Package Header files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+--
+-- VHDL Package Header %(library).%(unit)
+--
+-- Created:
+--          by - %(user).%(group) (%(host))
+--          at - %(time) %(date)
+--
+-- using Mentor Graphics HDL Designer(TM) %(version)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+PACKAGE %(entity_name) IS
+END %(entity_name);