Klagarge/SEm-ExamMidterm2024
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Rémi Heredero
2024-03-22 13:16:48 +01:00
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19
Prefs/hds_user/v2005.1/templates/registered_views/Vunit_VHDL.psl Normal file
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DESCRIPTION_START
This is the default template used for the creation of PSL Vunit (VHDL) files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- PSL Vunit(VHDL Syntax)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
vunit %(view) ([%(unit)])
{
default clock IS ClockName;
}

19
Prefs/hds_user/v2005.1/templates/registered_views/Vunit_Verilog.psl Normal file
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DESCRIPTION_START
This is the default template used for the creation of PSL Vunit (Verilog) files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// PSL Vunit(Verilog Syntax)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
vunit %(view) ([%(unit)])
{
default clock = ClockName;
}

13
Prefs/hds_user/v2005.1/templates/registered_views/c_file.c Normal file
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FILE_NAMING_RULE: c_file.c
DESCRIPTION_START
This is the default template used for the creation of C files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
/*
* Created:
* by - %(user).%(group) (%(host))
* at - %(time) %(date)
*
* using Mentor Graphics HDL Designer(TM) %(version)
*/

59
Prefs/hds_user/v2005.1/templates/registered_views/sc_source.cpp Normal file
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FILE_NAMING_RULE: %(unit).cpp
DESCRIPTION_START
This is the default template used for the creation of SystemC source files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
// Filename: %(view)
#include "systemc.h"
//#include "%(unit).h"
// Method body for %(unit)_action
void %(unit)::%(unit)_action()
{
}
SC_MODULE_EXPORT(%(unit));
//
// It is recommended that the SC_MODULE code is placed in a separate header file
// If required, you can copy/paste the following template code into a header file
// called %(unit).h and uncomment the #include statement above.
//#ifndef %(unit)_H
//#define %(unit)_H
//
//#include "systemc.h"
//
//SC_MODULE (%(unit))
//{
// // Ports
// sc_in<bool> clk,
// sc_in<int> in2;
// sc_out<int> out1;
//
// // Methods
// void %(unit)_action();
//
// // %(unit) Constructor
// SC_CTOR(%(unit))
// :
// {
// SC_THREAD(%(unit)_action);
// sensitive << clk.pos();
// }
//
// // %(unit) Destructor
// ~%(unit)
// {
// }
//
//};

14
Prefs/hds_user/v2005.1/templates/verilog_include/verilog_include.v Normal file
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FILE_NAMING_RULE: include_filename.v
DESCRIPTION_START
This is the default template used for the creation of Verilog Include files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Include file %(library)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//

18
Prefs/hds_user/v2005.1/templates/verilog_module/module.v Normal file
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FILE_NAMING_RULE: %(module_name).v
DESCRIPTION_START
This is the default template used for the creation of Verilog Module files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Verilog Module %(library).%(unit)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
%(moduleBody)
// ### Please start your Verilog code here ###
endmodule

22
Prefs/hds_user/v2005.1/templates/verilog_module/module_migrated.v Normal file
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FILE_NAMING_RULE: %(module_name).v
DESCRIPTION_START
Template for the creation of Verilog Module files.
This template was migrated from header preferences created in a
previous version of HDL Designer.
DESCRIPTION_END
//
//
// Module %(library).%(unit).%(view)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// Generated by Mentor Graphics' HDL Designer(TM) %(version)
//
//
%(moduleBody)
//
// ### Please start your Verilog code here ###
endmodule

15
Prefs/hds_user/v2005.1/templates/vhdl_architecture/architecture.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
Prefs/hds_user/v2005.1/templates/vhdl_combined/combined.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
Prefs/hds_user/v2005.1/templates/vhdl_configuration/configuration.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
Prefs/hds_user/v2005.1/templates/vhdl_entity/entity.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
Prefs/hds_user/v2005.1/templates/vhdl_package_body/package_body.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
Prefs/hds_user/v2005.1/templates/vhdl_package_header/package_header.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);