exercice 3

VHD/hdl/ex_24_1_3_entity.vhd

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+-- VHDL Entity VHD.ex_24_1_3.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 09:40:30 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_24_1_3 IS
+   GENERIC( 
+      timerBitNb    : positive := 8;
+      testModeBitNb : positive := 1
+   );
+   PORT( 
+      testMode : IN     std_ulogic;
+      clock    : IN     std_ulogic;
+      reset    : IN     std_ulogic;
+      pwmEn    : OUT    std_ulogic
+   );
+
+-- Declarations
+
+END ex_24_1_3 ;
+