exercice 3

VHD/hdl/ex_24_1_3_entity.vhd

@@ -0,0 +1,28 @@
+-- VHDL Entity VHD.ex_24_1_3.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 09:40:30 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_24_1_3 IS
+   GENERIC( 
+      timerBitNb    : positive := 8;
+      testModeBitNb : positive := 1
+   );
+   PORT( 
+      testMode : IN     std_ulogic;
+      clock    : IN     std_ulogic;
+      reset    : IN     std_ulogic;
+      pwmEn    : OUT    std_ulogic
+   );
+
+-- Declarations
+
+END ex_24_1_3 ;
+

VHD/hdl/ex_24_1_3_studentVersion.vhd

@@ -1,4 +1,28 @@
 architecture studentVersion of ex_24_1_3 is
+
+  signal counter : unsigned(timerBitNb-1 downto 0);
+
 begin
-  pwmEn <= '0';
+
+  process(reset, clock) begin
+    if reset = '1' then 
+      counter <= (others => '0');
+    elsif rising_edge(clock) then 
+      if testMode = '0' then
+        counter <= counter - 1;
+      else
+        counter <= counter - 2**(timerBitNb - testModeBitNb);
+      end if;
+    end if;
+  end process;
+
+  process(counter)
+  begin
+    if counter = 0 then
+      pwmEn <= '1';
+    else
+      pwmEn <= '0';
+    end if;
+  end process;
+
 end studentVersion;