mirror of
https://github.com/Klagarge/Cursor.git
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1650 lines
21 KiB
Plaintext
1650 lines
21 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
|
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ldm (LogicalDM
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suid 2005,0
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|
usingSuid 1
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emptyRow *1 (LEmptyRow
|
|
)
|
|
uid 199,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
|
|
decl (Decl
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|
n "clock"
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t "std_uLogic"
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o 1
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suid 1,0
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)
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)
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|
uid 200,0
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)
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*3 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "up"
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|
t "std_uLogic"
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|
o 5
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suid 5,0
|
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)
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)
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|
uid 201,0
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)
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*4 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "down"
|
|
t "std_uLogic"
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|
o 4
|
|
suid 4,0
|
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)
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|
)
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|
uid 202,0
|
|
)
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|
*5 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_uLogic"
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|
o 3
|
|
suid 3,0
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)
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)
|
|
uid 203,0
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|
)
|
|
*6 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "countOut"
|
|
t "unsigned"
|
|
b "(bitNb-1 DOWNTO 0)"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 204,0
|
|
)
|
|
*7 (RefLabelRowHdr
|
|
)
|
|
*8 (TitleRowHdr
|
|
)
|
|
*9 (FilterRowHdr
|
|
)
|
|
*10 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*11 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*12 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*13 (NameColHdr
|
|
tm "NameColHdrMgr"
|
|
)
|
|
*14 (ModeColHdr
|
|
tm "ModeColHdrMgr"
|
|
)
|
|
*15 (TypeColHdr
|
|
tm "TypeColHdrMgr"
|
|
)
|
|
*16 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
|
|
)
|
|
*17 (InitColHdr
|
|
tm "InitColHdrMgr"
|
|
)
|
|
*18 (EolColHdr
|
|
tm "EolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 205,0
|
|
optionalChildren [
|
|
*19 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *20 (MRCItem
|
|
litem &1
|
|
pos 5
|
|
dimension 20
|
|
)
|
|
uid 140,0
|
|
optionalChildren [
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|
*21 (MRCItem
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|
litem &7
|
|
pos 0
|
|
dimension 20
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uid 143,0
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|
)
|
|
*22 (MRCItem
|
|
litem &8
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pos 1
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dimension 23
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uid 145,0
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)
|
|
*23 (MRCItem
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litem &9
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pos 2
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hidden 1
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|
dimension 20
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|
uid 147,0
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|
)
|
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*24 (MRCItem
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|
litem &2
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pos 0
|
|
dimension 20
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uid 166,0
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|
)
|
|
*25 (MRCItem
|
|
litem &3
|
|
pos 3
|
|
dimension 20
|
|
uid 167,0
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)
|
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*26 (MRCItem
|
|
litem &4
|
|
pos 1
|
|
dimension 20
|
|
uid 168,0
|
|
)
|
|
*27 (MRCItem
|
|
litem &5
|
|
pos 2
|
|
dimension 20
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|
uid 169,0
|
|
)
|
|
*28 (MRCItem
|
|
litem &6
|
|
pos 4
|
|
dimension 20
|
|
uid 170,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
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|
)
|
|
uid 141,0
|
|
optionalChildren [
|
|
*29 (MRCItem
|
|
litem &10
|
|
pos 0
|
|
dimension 20
|
|
uid 149,0
|
|
)
|
|
*30 (MRCItem
|
|
litem &12
|
|
pos 1
|
|
dimension 50
|
|
uid 153,0
|
|
)
|
|
*31 (MRCItem
|
|
litem &13
|
|
pos 2
|
|
dimension 100
|
|
uid 155,0
|
|
)
|
|
*32 (MRCItem
|
|
litem &14
|
|
pos 3
|
|
dimension 50
|
|
uid 157,0
|
|
)
|
|
*33 (MRCItem
|
|
litem &15
|
|
pos 4
|
|
dimension 100
|
|
uid 159,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &16
|
|
pos 5
|
|
dimension 100
|
|
uid 161,0
|
|
)
|
|
*35 (MRCItem
|
|
litem &17
|
|
pos 6
|
|
dimension 50
|
|
uid 163,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &18
|
|
pos 7
|
|
dimension 80
|
|
uid 165,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 139,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 198,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *37 (LEmptyRow
|
|
)
|
|
uid 207,0
|
|
optionalChildren [
|
|
*38 (RefLabelRowHdr
|
|
)
|
|
*39 (TitleRowHdr
|
|
)
|
|
*40 (FilterRowHdr
|
|
)
|
|
*41 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*42 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*43 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*44 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*45 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*46 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*47 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*48 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*49 (LogGeneric
|
|
generic (GiElement
|
|
name "bitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 196,0
|
|
)
|
|
*50 (LogGeneric
|
|
generic (GiElement
|
|
name "delay"
|
|
type "time"
|
|
value "gateDelay"
|
|
)
|
|
uid 310,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 208,0
|
|
optionalChildren [
|
|
*51 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *52 (MRCItem
|
|
litem &37
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 172,0
|
|
optionalChildren [
|
|
*53 (MRCItem
|
|
litem &38
|
|
pos 0
|
|
dimension 20
|
|
uid 175,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &39
|
|
pos 1
|
|
dimension 23
|
|
uid 177,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &40
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 179,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &49
|
|
pos 1
|
|
dimension 20
|
|
uid 197,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &50
|
|
pos 0
|
|
dimension 20
|
|
uid 311,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 173,0
|
|
optionalChildren [
|
|
*58 (MRCItem
|
|
litem &41
|
|
pos 0
|
|
dimension 20
|
|
uid 181,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &43
|
|
pos 1
|
|
dimension 50
|
|
uid 185,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
dimension 100
|
|
uid 187,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &45
|
|
pos 3
|
|
dimension 100
|
|
uid 189,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &46
|
|
pos 4
|
|
dimension 50
|
|
uid 191,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &47
|
|
pos 5
|
|
dimension 50
|
|
uid 193,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &48
|
|
pos 6
|
|
dimension 80
|
|
uid 195,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 171,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 206,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/counter@up@down/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/counter@up@down/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/counter@up@down"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/counterUpDown"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "counterUpDown"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:46:19"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "sequential"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Libraries/sequential/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "counterUpDown"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Aug"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "August"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/counter@up@down/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/counterUpDown/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelPath"
|
|
value "$ACTEL_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelProjectPath"
|
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ACTEL_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelUserPath"
|
|
value "$HDS_PROJECT_DIR\\..\\$ACTEL_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\Board\\ise"
|
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