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76 lines
2.4 KiB
VHDL
76 lines
2.4 KiB
VHDL
-- ------------------------------------------------------------------------------
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-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch)
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-- ------------------------------------------------------------------------------
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-- FIFO bridge with bus width adaption
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-- A shift register that connects two FIFOs with different bus width.
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-- Many IP blocks nowadays have FIFO or FIFO-like interface. But the bus width
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-- varies often. This block can the be used to adapt the bus width to your own
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-- needs.
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-- The Tx side bus width has to be a multiple of the Rx side bus width.
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--
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-- Created on 2013-10-21
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--
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-- Version: 1.0
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-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
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-- ------------------------------------------------------------------------------
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--
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library common;
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use common.commonlib.all;
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ARCHITECTURE behavioral OF fifoBridgeRxToTxBusWidthAdaptionTxbigger IS
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constant ratio_txrx_c: positive range 1 to dataBitNbTx/dataBitNbRx:= dataBitNbTx/dataBitNbRx;
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signal cnt_s: unsigned(requiredBitNb(ratio_txrx_c-1)-1 downto 0);
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signal shiftreg_s: std_ulogic_vector(dataBitNbTx-1 downto 0);
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signal fullTx_s: std_ulogic;
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signal emptyRx_s: std_ulogic;
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BEGIN
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rx0: process(clock, reset)
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begin
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if reset = '1' then
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shiftreg_s <= (others => '0');
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readRx <= '1';
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emptyRx_s <= '1';
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cnt_s <= (others => '0');
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elsif rising_edge(clock) then
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readRx <= NOT fullTx_s;
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emptyRx_s <= '1';
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if emptyRx = '0' and fullTx_s = '0' then
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-- shiftreg_s(((to_integer(cnt_s)+1)*dataBitNbRx)-1 downto to_integer(cnt_s)*dataBitNbRx) <= dataRx;
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shiftreg_s <= shiftreg_s(dataBitNbTx-dataBitNbRx-1 downto 0) & dataRx;
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readRx <= '1';
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cnt_s <= cnt_s +1;
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if cnt_s >= ratio_txrx_c-1 then
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cnt_s <= (others => '0');
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emptyRx_s <= '0';
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end if;
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end if;
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end if;
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end process;
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tx0: process(clock, reset)
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begin
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if reset = '1' then
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fullTx_s <= '1';
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writeTx <= '0';
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dataTx <= (others => '0');
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elsif rising_edge(clock) then
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fullTx_s <= fullTx;
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writeTx <= '0';
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-- no need to wait to check for full (in contrast to RxBigger)
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-- because it will forcibly take several clocks to fill the shiftreg
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if emptyRx_s = '0' and fullTx = '0' then
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dataTx <= shiftreg_s;
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writeTx <= '1';
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end if;
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end if;
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end process;
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END ARCHITECTURE behavioral;
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