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44 lines
1.3 KiB
VHDL
44 lines
1.3 KiB
VHDL
ARCHITECTURE sim OF mux2to1 IS
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subtype tSelect is std_uLogic_vector(0 to 2);
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BEGIN
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muxSelect: process(sel, in0, in1)
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begin
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if sel = '1' then
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muxOut <= in1 after delay;
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elsif sel = '0' then
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muxOut <= in0 after delay;
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else
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muxOut <= 'X' after delay;
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end if;
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end process muxSelect;
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-- muxSelect: process(sel, in0, in1)
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-- begin
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-- -- case tSelect'(to_X01(sel & in0 & in1)) is
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-- case to_X01(tSelect'(sel & in0 & in1)) is
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-- -- select in0
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-- when "000" => muxOut <= '0' after delay;
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-- when "001" => muxOut <= '0' after delay;
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-- when "00X" => muxOut <= '0' after delay;
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-- when "010" => muxOut <= '1' after delay;
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-- when "011" => muxOut <= '1' after delay;
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-- when "01X" => muxOut <= '1' after delay;
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-- -- select in1
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-- when "100" => muxOut <= '0' after delay;
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-- when "110" => muxOut <= '0' after delay;
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-- when "1X0" => muxOut <= '0' after delay;
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-- when "101" => muxOut <= '1' after delay;
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-- when "111" => muxOut <= '1' after delay;
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-- when "1X1" => muxOut <= '1' after delay;
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-- -- select in0 equal to in1
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-- when "X00" => muxOut <= '0' after delay;
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-- when "X11" => muxOut <= '1' after delay;
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-- -- others
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-- when others => muxOut <= 'X' after delay;
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-- end case;
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-- end process muxSelect;
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END ARCHITECTURE sim;
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