mirror of
https://github.com/Klagarge/Cursor.git
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1779 lines
22 KiB
Plaintext
1779 lines
22 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 14,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 151,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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|
*4 (FilterRowHdr
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)
|
|
*5 (RefLabelColHdr
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|
tm "RefLabelColHdrMgr"
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)
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|
*6 (RowExpandColHdr
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|
tm "RowExpandColHdrMgr"
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)
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|
*7 (GroupColHdr
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|
tm "GroupColHdrMgr"
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|
)
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|
*8 (NameColHdr
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|
tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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|
tm "ModeColHdrMgr"
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|
)
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|
*10 (TypeColHdr
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|
tm "TypeColHdrMgr"
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)
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|
*11 (BoundsColHdr
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|
tm "BoundsColHdrMgr"
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)
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|
*12 (InitColHdr
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|
tm "InitColHdrMgr"
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)
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|
*13 (EolColHdr
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|
tm "EolColHdrMgr"
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)
|
|
*14 (LogPort
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port (LogicalPort
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|
lang 11
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 1,0
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)
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)
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|
uid 51,0
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)
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*15 (LogPort
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port (LogicalPort
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|
lang 11
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|
decl (Decl
|
|
n "writeEn"
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t "std_ulogic"
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o 3
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suid 4,0
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)
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)
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uid 57,0
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)
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*16 (LogPort
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port (LogicalPort
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|
lang 11
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decl (Decl
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|
n "addressIn"
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t "std_ulogic_vector"
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|
b "(addressBitNb-1 DOWNTO 0)"
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o 4
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suid 5,0
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)
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)
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uid 59,0
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)
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*17 (LogPort
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port (LogicalPort
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|
lang 11
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|
decl (Decl
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|
n "dataIn"
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t "std_ulogic_vector"
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|
b "(dataBitNb-1 DOWNTO 0)"
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o 5
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suid 6,0
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)
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)
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uid 61,0
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)
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*18 (LogPort
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port (LogicalPort
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|
lang 11
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|
m 1
|
|
decl (Decl
|
|
n "dataOut"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
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posAdd 0
|
|
o 6
|
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suid 7,0
|
|
)
|
|
)
|
|
uid 63,0
|
|
)
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|
*19 (LogPort
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|
port (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "en"
|
|
t "std_ulogic"
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o 2
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suid 3,0
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)
|
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)
|
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uid 55,0
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)
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]
|
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)
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pdm (PhysicalDM
|
|
displayShortBounds 1
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|
editShortBounds 1
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uid 164,0
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|
optionalChildren [
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*20 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
|
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cellColor "65535,65535,65535"
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|
fontColor "0,0,0"
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font "courier,10,0"
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)
|
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groupVa (MVa
|
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *21 (MRCItem
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litem &1
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pos 6
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dimension 20
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)
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uid 166,0
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optionalChildren [
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*22 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 167,0
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)
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*23 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 168,0
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)
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*24 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 169,0
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)
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*25 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 52,0
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)
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*26 (MRCItem
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litem &15
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pos 2
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dimension 20
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uid 58,0
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)
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*27 (MRCItem
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litem &16
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pos 3
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dimension 20
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uid 60,0
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)
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*28 (MRCItem
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litem &17
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pos 4
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dimension 20
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uid 62,0
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)
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*29 (MRCItem
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litem &18
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pos 5
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dimension 20
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uid 64,0
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)
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*30 (MRCItem
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litem &19
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pos 1
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dimension 20
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uid 56,0
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)
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]
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)
|
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sheetCol (SheetCol
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|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
|
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uid 170,0
|
|
optionalChildren [
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|
*31 (MRCItem
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litem &5
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pos 0
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dimension 20
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|
uid 171,0
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)
|
|
*32 (MRCItem
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|
litem &7
|
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pos 1
|
|
dimension 50
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|
uid 172,0
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)
|
|
*33 (MRCItem
|
|
litem &8
|
|
pos 2
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|
dimension 100
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|
uid 173,0
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|
)
|
|
*34 (MRCItem
|
|
litem &9
|
|
pos 3
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|
dimension 50
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|
uid 174,0
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)
|
|
*35 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 175,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 176,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 177,0
|
|
)
|
|
*38 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 178,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 165,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 150,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *39 (LEmptyRow
|
|
)
|
|
uid 180,0
|
|
optionalChildren [
|
|
*40 (RefLabelRowHdr
|
|
)
|
|
*41 (TitleRowHdr
|
|
)
|
|
*42 (FilterRowHdr
|
|
)
|
|
*43 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*44 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*45 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*46 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*47 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*48 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*49 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*50 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*51 (LogGeneric
|
|
generic (GiElement
|
|
name "addressBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 439,0
|
|
)
|
|
*52 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 441,0
|
|
)
|
|
*53 (LogGeneric
|
|
generic (GiElement
|
|
name "initFile"
|
|
type "string"
|
|
value "\"bramInit.txt\""
|
|
)
|
|
uid 443,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 192,0
|
|
optionalChildren [
|
|
*54 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *55 (MRCItem
|
|
litem &39
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 194,0
|
|
optionalChildren [
|
|
*56 (MRCItem
|
|
litem &40
|
|
pos 0
|
|
dimension 20
|
|
uid 195,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &41
|
|
pos 1
|
|
dimension 23
|
|
uid 196,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &42
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 197,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &51
|
|
pos 0
|
|
dimension 20
|
|
uid 440,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &52
|
|
pos 1
|
|
dimension 20
|
|
uid 442,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &53
|
|
pos 2
|
|
dimension 20
|
|
uid 444,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 198,0
|
|
optionalChildren [
|
|
*62 (MRCItem
|
|
litem &43
|
|
pos 0
|
|
dimension 20
|
|
uid 199,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &45
|
|
pos 1
|
|
dimension 50
|
|
uid 200,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &46
|
|
pos 2
|
|
dimension 100
|
|
uid 201,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &47
|
|
pos 3
|
|
dimension 100
|
|
uid 202,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &48
|
|
pos 4
|
|
dimension 86
|
|
uid 203,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &49
|
|
pos 5
|
|
dimension 50
|
|
uid 204,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &50
|
|
pos 6
|
|
dimension 80
|
|
uid 205,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 193,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 179,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hds/bram/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hds/bram/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hds/bram"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hds/bram"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "02/19/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Tue"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Tuesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "19"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "bram"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "02/19/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:42:23"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Memory"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Memory"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "02"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "bram"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Feb"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "February"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hds/bram/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/HiRel/FPGA/Libs/Memory/hds/bram/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "cansat"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:42:23"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "bram"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 149,0
|
|
optionalChildren [
|
|
*69 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*70 (CptPort
|
|
uid 79,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 80,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,26625,39000,27375"
|
|
)
|
|
tg (CPTG
|
|
uid 81,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 82,0
|
|
va (VaSet
|
|
)
|
|
xt "40000,26500,43000,27500"
|
|
st "clock"
|
|
blo "40000,27300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 83,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,9200,18500,10100"
|
|
st "clock : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*71 (CptPort
|
|
uid 89,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 90,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,24625,39000,25375"
|
|
)
|
|
tg (CPTG
|
|
uid 91,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 92,0
|
|
va (VaSet
|
|
)
|
|
xt "40000,24500,41200,25500"
|
|
st "en"
|
|
blo "40000,25300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 93,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,10100,18500,11000"
|
|
st "en : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "en"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*72 (CptPort
|
|
uid 94,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 95,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,20625,39000,21375"
|
|
)
|
|
tg (CPTG
|
|
uid 96,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 97,0
|
|
va (VaSet
|
|
)
|
|
xt "40000,20500,44200,21500"
|
|
st "writeEn"
|
|
blo "40000,21300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 98,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,11000,18500,11900"
|
|
st "writeEn : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "writeEn"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*73 (CptPort
|
|
uid 99,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 100,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,14625,39000,15375"
|
|
)
|
|
tg (CPTG
|
|
uid 101,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 102,0
|
|
va (VaSet
|
|
)
|
|
xt "40000,14500,45400,15500"
|
|
st "addressIn"
|
|
blo "40000,15300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 103,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,11900,34500,12800"
|
|
st "addressIn : IN std_ulogic_vector (addressBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "addressIn"
|
|
t "std_ulogic_vector"
|
|
b "(addressBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*74 (CptPort
|
|
uid 104,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 105,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,18625,39000,19375"
|
|
)
|
|
tg (CPTG
|
|
uid 106,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 107,0
|
|
va (VaSet
|
|
)
|
|
xt "40000,18500,43600,19500"
|
|
st "dataIn"
|
|
blo "40000,19300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 108,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,12800,33000,13700"
|
|
st "dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "dataIn"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
*75 (CptPort
|
|
uid 109,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 206,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,16625,39000,17375"
|
|
)
|
|
tg (CPTG
|
|
uid 111,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 112,0
|
|
va (VaSet
|
|
)
|
|
xt "40000,16500,44200,17500"
|
|
st "dataOut"
|
|
blo "40000,17300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 113,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,13700,32000,14600"
|
|
st "dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0)
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "dataOut"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
posAdd 0
|
|
o 6
|
|
suid 7,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 9,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "39000,11000,55000,29000"
|
|
)
|
|
oxt "15000,6000,33000,36000"
|
|
biTextGroup (BiTextGroup
|
|
uid 10,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
uid 11,0
|
|
va (VaSet
|
|
font "courier,8,1"
|
|
)
|
|
xt "39200,29000,42200,29900"
|
|
st "Memory"
|
|
blo "39200,29700"
|
|
)
|
|
second (Text
|
|
uid 12,0
|
|
va (VaSet
|
|
font "courier,8,1"
|
|
)
|
|
xt "39200,29900,41200,30800"
|
|
st "bram"
|
|
blo "39200,30600"
|
|
)
|
|
)
|
|
gi *76 (GenericInterface
|
|
uid 13,0
|
|
ps "CenterOffsetStrategy"
|
|
matrix (Matrix
|
|
uid 14,0
|
|
text (MLText
|
|
uid 15,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "39000,32000,58500,36500"
|
|
st "Generic Declarations
|
|
|
|
addressBitNb positive 8
|
|
dataBitNb positive 8
|
|
initFile string \"bramInit.txt\" "
|
|
)
|
|
header "Generic Declarations"
|
|
showHdrWhenContentsEmpty 1
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "addressBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
(GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
(GiElement
|
|
name "initFile"
|
|
type "string"
|
|
value "\"bramInit.txt\""
|
|
)
|
|
]
|
|
)
|
|
portInstanceVisAsIs 1
|
|
portInstanceVis (PortSigDisplay
|
|
sTC 0
|
|
sIVOD 1
|
|
)
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
sIVOD 1
|
|
)
|
|
)
|
|
*77 (Grouping
|
|
uid 16,0
|
|
optionalChildren [
|
|
*78 (CommentText
|
|
uid 18,0
|
|
shape (Rectangle
|
|
uid 19,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "36000,48000,53000,49000"
|
|
)
|
|
oxt "18000,70000,35000,71000"
|
|
text (MLText
|
|
uid 20,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "36200,48000,52400,49000"
|
|
st "
|
|
by %user on %dd %month %year
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*79 (CommentText
|
|
uid 21,0
|
|
shape (Rectangle
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|
uid 22,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
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|
|
)
|
|
oxt "35000,66000,39000,67000"
|
|
text (MLText
|
|
uid 23,0
|
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va (VaSet
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|
fg "0,0,32768"
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|
bg "0,0,32768"
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|
)
|
|
xt "53200,44000,56800,45000"
|
|
st "
|
|
Project:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
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|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*80 (CommentText
|
|
uid 24,0
|
|
shape (Rectangle
|
|
uid 25,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "36000,46000,53000,47000"
|
|
)
|
|
oxt "18000,68000,35000,69000"
|
|
text (MLText
|
|
uid 26,0
|
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va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "36200,46000,52400,47000"
|
|
st "
|
|
<enter diagram title here>
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*81 (CommentText
|
|
uid 27,0
|
|
shape (Rectangle
|
|
uid 28,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "32000,46000,36000,47000"
|
|
)
|
|
oxt "14000,68000,18000,69000"
|
|
text (MLText
|
|
uid 29,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "32200,46000,35800,47000"
|
|
st "
|
|
Title:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*82 (CommentText
|
|
uid 30,0
|
|
shape (Rectangle
|
|
uid 31,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "53000,45000,73000,49000"
|
|
)
|
|
oxt "35000,67000,55000,71000"
|
|
text (MLText
|
|
uid 32,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
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|
|
st "
|
|
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|
|
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|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 4000
|
|
visibleWidth 20000
|
|
)
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
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|
|
uid 33,0
|
|
shape (Rectangle
|
|
uid 34,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "57000,44000,73000,45000"
|
|
)
|
|
oxt "39000,66000,55000,67000"
|
|
text (MLText
|
|
uid 35,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
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