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34 lines
1.0 KiB
VHDL
34 lines
1.0 KiB
VHDL
ARCHITECTURE sim OF mux16to1 IS
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BEGIN
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P1: process(sel,
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in0, in1, in2, in3,
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in4, in5, in6, in7,
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in8, in9, in10, in11,
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in12, in13, in14, in15
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)
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begin
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case to_integer(sel) is
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when 0 => muxOut <= in0 after delay;
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when 1 => muxOut <= in1 after delay;
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when 2 => muxOut <= in2 after delay;
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when 3 => muxOut <= in3 after delay;
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when 4 => muxOut <= in4 after delay;
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when 5 => muxOut <= in5 after delay;
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when 6 => muxOut <= in6 after delay;
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when 7 => muxOut <= in7 after delay;
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when 8 => muxOut <= in8 after delay;
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when 9 => muxOut <= in9 after delay;
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when 10 => muxOut <= in10 after delay;
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when 11 => muxOut <= in11 after delay;
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when 12 => muxOut <= in12 after delay;
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when 13 => muxOut <= in13 after delay;
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when 14 => muxOut <= in14 after delay;
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when 15 => muxOut <= in15 after delay;
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when others => null;
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end case;
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end process P1;
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END ARCHITECTURE sim;
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