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18 lines
343 B
VHDL
18 lines
343 B
VHDL
ARCHITECTURE RTL OF sdramControllerSampleDataIn IS
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BEGIN
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sampleRamData: process(reset, clock)
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begin
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if reset = '1' then
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ramDataIn <= (others => '0');
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elsif falling_edge(clock) then
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if sampleData = '1' then
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ramDataIn <= memDataIn;
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end if;
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end if;
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end process sampleRamData;
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END ARCHITECTURE RTL;
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