mirror of
https://github.com/Klagarge/Cursor.git
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3527 lines
43 KiB
Plaintext
3527 lines
43 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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instances [
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|
(Instance
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name "I_tester"
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duLibraryName "Lcd_test"
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duName "lcdDemo_tester"
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elements [
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|
(GiElement
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|
name "clockFrequency"
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|
type "real"
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value "clockFrequency"
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)
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|
(GiElement
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|
name "buttonNb"
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|
type "positive"
|
|
value "buttonNb"
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)
|
|
(GiElement
|
|
name "ledNb"
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|
type "positive"
|
|
value "ledNb"
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|
)
|
|
(GiElement
|
|
name "baudrate"
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|
type "positive"
|
|
value "rs232Baudrate"
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|
)
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|
]
|
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mwi 0
|
|
uid 175,0
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|
)
|
|
(Instance
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|
name "I_dut"
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|
duLibraryName "lcd"
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duName "lcdDemo"
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|
elements [
|
|
(GiElement
|
|
name "baudRateDivide"
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|
type "positive"
|
|
value "baudRateDivide"
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|
)
|
|
(GiElement
|
|
name "buttonNb"
|
|
type "positive"
|
|
value "buttonNb"
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|
)
|
|
(GiElement
|
|
name "ledNb"
|
|
type "positive"
|
|
value "ledNb"
|
|
)
|
|
(GiElement
|
|
name "rs232BaudRate"
|
|
type "positive"
|
|
value "rs232Baudrate"
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)
|
|
]
|
|
mwi 0
|
|
uid 4057,0
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|
)
|
|
]
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|
libraryRefs [
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|
"ieee"
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|
]
|
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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|
model (BlockDiag
|
|
VExpander (VariableExpander
|
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vvMap [
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|
(vvPair
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|
variable " "
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|
value " "
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)
|
|
(vvPair
|
|
variable "HDLDir"
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|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hdl"
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|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@demo_tb\\struct.bd.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@demo_tb\\struct.bd.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@demo_tb"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdDemo_tb"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "11.11.2019"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Mon"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Monday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "lcdDemo_tb"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.11.2019"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "07:37:47"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
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|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Lcd_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../libs/SPI_test/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/ElN/Libraries/Lcd_test/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "11"
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)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "lcdDemo_tb"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Nov"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "November"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@demo_tb\\struct.bd"
|
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)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdDemo_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelPath"
|
|
value "D:\\Projects\\Trypano\\ControlBoard\\IglooTester\\Board\\actel\\boardTester"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$SCRATCH_DIR\\BoardTester\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "07:37:47"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "lcdDemo_tb"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
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)
|
|
(vvPair
|
|
variable "view"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
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)
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]
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)
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uid 20,0
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va (VaSet
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)
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)
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oxt "13000,28000,18000,30000"
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text (MLText
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uid 108,0
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bg "0,0,32768"
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)
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xt "46200,64400,50500,65600"
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st "
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Edited:
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tm "CommentText"
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wrapOption 3
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visibleWidth 4600
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)
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shape (GroupingShape
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)
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xt "46000,58000,97000,66000"
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)
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oxt "13000,22000,64000,30000"
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shape (Rectangle
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uid 176,0
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va (VaSet
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)
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oxt "24000,40000,84000,48000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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blo "29300,49200"
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tm "BdLibraryNameMgr"
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xt "29300,49700,36800,50600"
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)
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xt "29300,50900,33300,51800"
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)
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ga (GenericAssociation
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uid 181,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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uid 182,0
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text (MLText
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uid 183,0
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va (VaSet
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xt "29000,52600,55200,57400"
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st "clockFrequency = clockFrequency ( real )
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buttonNb = buttonNb ( positive )
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header ""
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value "clockFrequency"
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)
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name "buttonNb"
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type "positive"
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value "buttonNb"
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)
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(GiElement
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name "ledNb"
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type "positive"
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value "ledNb"
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)
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(GiElement
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name "baudrate"
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type "positive"
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value "rs232Baudrate"
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)
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viewicon (ZoomableIcon
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uid 184,0
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va (VaSet
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va (VaSet
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font "Verdana,8,0"
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xt "2000,24800,14300,25800"
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decl (Decl
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n "clock"
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t "std_ulogic"
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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xt "2000,22800,14300,23800"
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uid 3041,0
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decl (Decl
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n "CS1_n"
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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uid 3049,0
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decl (Decl
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n "RST_n"
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t "std_ulogic"
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,17800,14900,18800"
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uid 3057,0
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decl (Decl
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n "A0"
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t "std_ulogic"
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o 1
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)
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declText (MLText
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uid 3058,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,15800,14200,16800"
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st "SIGNAL A0 : std_ulogic"
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uid 3065,0
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decl (Decl
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n "SCL"
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t "std_ulogic"
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o 5
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)
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,19800,14400,20800"
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)
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)
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*22 (Net
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uid 3073,0
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decl (Decl
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n "SI"
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t "std_ulogic"
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o 6
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suid 51,0
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)
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declText (MLText
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uid 3074,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,20800,14000,21800"
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st "SIGNAL SI : std_ulogic"
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)
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)
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*23 (Net
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uid 3706,0
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decl (Decl
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n "buttons"
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t "std_ulogic_vector"
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b "(1 to buttonNb)"
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o 7
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suid 56,0
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)
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declText (MLText
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uid 3707,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,21800,24600,22800"
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st "SIGNAL buttons : std_ulogic_vector(1 to buttonNb)"
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)
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)
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*24 (Net
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uid 3714,0
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decl (Decl
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n "leds"
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t "std_ulogic_vector"
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b "(1 to ledNb)"
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o 9
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suid 57,0
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)
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declText (MLText
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uid 3715,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,23800,22700,24800"
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st "SIGNAL leds : std_ulogic_vector(1 to ledNb)"
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)
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*25 (Net
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uid 3817,0
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decl (Decl
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n "RxD"
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t "std_ulogic"
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o 4
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suid 58,0
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)
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declText (MLText
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uid 3818,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,18800,14600,19800"
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st "SIGNAL RxD : std_ulogic"
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*26 (SaComponent
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uid 4057,0
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optionalChildren [
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*27 (CptPort
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uid 4013,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 4014,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "44250,27625,45000,28375"
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)
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tg (CPTG
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uid 4015,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 4016,0
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va (VaSet
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)
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|
xt "46000,27400,48500,28300"
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|
st "clock"
|
|
blo "46000,28100"
|
|
)
|
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)
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thePort (LogicalPort
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decl (Decl
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n "clock"
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|
t "std_ulogic"
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|
o 7
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|
suid 1,0
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)
|
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)
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)
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*28 (CptPort
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uid 4017,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 4018,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
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uid 4019,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 4020,0
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va (VaSet
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)
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xt "46000,29400,48500,30300"
|
|
st "reset"
|
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blo "46000,30100"
|
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)
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)
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thePort (LogicalPort
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|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
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|
o 1
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|
suid 2,0
|
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)
|
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)
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)
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*29 (CptPort
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uid 4021,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 4022,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "61000,19625,61750,20375"
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)
|
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tg (CPTG
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|
uid 4023,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 4024,0
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va (VaSet
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)
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|
xt "59000,19400,60000,20300"
|
|
st "SI"
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ju 2
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|
blo "60000,20100"
|
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)
|
|
)
|
|
thePort (LogicalPort
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|
m 1
|
|
decl (Decl
|
|
n "SI"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*30 (CptPort
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|
uid 4025,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 4026,0
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ro 90
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|
va (VaSet
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|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,21625,61750,22375"
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)
|
|
tg (CPTG
|
|
uid 4027,0
|
|
ps "CptPortTextPlaceStrategy"
|
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stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 4028,0
|
|
va (VaSet
|
|
)
|
|
xt "58500,21400,60000,22300"
|
|
st "SCL"
|
|
ju 2
|
|
blo "60000,22100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "SCL"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*31 (CptPort
|
|
uid 4029,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 4030,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,23625,61750,24375"
|
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)
|
|
tg (CPTG
|
|
uid 4031,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 4032,0
|
|
va (VaSet
|
|
)
|
|
xt "59000,23400,60000,24300"
|
|
st "A0"
|
|
ju 2
|
|
blo "60000,24100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "A0"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*32 (CptPort
|
|
uid 4033,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 4034,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "44250,15625,45000,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 4035,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 4036,0
|
|
va (VaSet
|
|
)
|
|
xt "46000,15400,49500,16300"
|
|
st "buttons"
|
|
blo "46000,16100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "buttons"
|
|
t "std_ulogic_vector"
|
|
b "(1 to buttonNb)"
|
|
o 8
|
|
suid 11,0
|
|
)
|
|
)
|
|
)
|
|
*33 (CptPort
|
|
uid 4037,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 4038,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,27625,61750,28375"
|
|
)
|
|
tg (CPTG
|
|
uid 4039,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 4040,0
|
|
va (VaSet
|
|
)
|
|
xt "57500,27400,60000,28300"
|
|
st "CS1_n"
|
|
ju 2
|
|
blo "60000,28100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "CS1_n"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 27,0
|
|
)
|
|
)
|
|
)
|
|
*34 (CptPort
|
|
uid 4041,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 4042,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,25625,61750,26375"
|
|
)
|
|
tg (CPTG
|
|
uid 4043,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 4044,0
|
|
va (VaSet
|
|
)
|
|
xt "57500,25400,60000,26300"
|
|
st "RST_n"
|
|
ju 2
|
|
blo "60000,26100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "RST_n"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 28,0
|
|
)
|
|
)
|
|
)
|
|
*35 (CptPort
|
|
uid 4045,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 4046,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,15625,61750,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 4047,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 4048,0
|
|
va (VaSet
|
|
)
|
|
xt "58000,15400,60000,16300"
|
|
st "leds"
|
|
ju 2
|
|
blo "60000,16100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "leds"
|
|
t "std_ulogic_vector"
|
|
b "(1 to ledNb)"
|
|
o 9
|
|
suid 30,0
|
|
)
|
|
)
|
|
)
|
|
*36 (CptPort
|
|
uid 4049,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 4050,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "44250,19625,45000,20375"
|
|
)
|
|
tg (CPTG
|
|
uid 4051,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 4052,0
|
|
va (VaSet
|
|
)
|
|
xt "46000,19400,47500,20300"
|
|
st "RxD"
|
|
blo "46000,20100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "RxD"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 31,0
|
|
)
|
|
)
|
|
)
|
|
*37 (CptPort
|
|
uid 4053,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 4054,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,29625,61750,30375"
|
|
)
|
|
tg (CPTG
|
|
uid 4055,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 4056,0
|
|
va (VaSet
|
|
)
|
|
xt "57500,29400,60000,30300"
|
|
st "debug"
|
|
ju 2
|
|
blo "60000,30100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "debug"
|
|
t "std_ulogic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 11
|
|
suid 32,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 4058,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "45000,12000,61000,32000"
|
|
)
|
|
oxt "8000,8000,24000,28000"
|
|
ttg (MlTextGroup
|
|
uid 4059,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*38 (Text
|
|
uid 4060,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "45600,31800,47100,32700"
|
|
st "lcd"
|
|
blo "45600,32500"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*39 (Text
|
|
uid 4061,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "45600,33000,49100,33900"
|
|
st "lcdDemo"
|
|
blo "45600,33700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*40 (Text
|
|
uid 4062,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "45600,34200,48100,35100"
|
|
st "I_dut"
|
|
blo "45600,34900"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 4063,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 4064,0
|
|
text (MLText
|
|
uid 4065,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "45000,35800,67400,39800"
|
|
st "baudRateDivide = baudRateDivide ( positive )
|
|
buttonNb = buttonNb ( positive )
|
|
ledNb = ledNb ( positive )
|
|
rs232BaudRate = rs232Baudrate ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "baudRateDivide"
|
|
type "positive"
|
|
value "baudRateDivide"
|
|
)
|
|
(GiElement
|
|
name "buttonNb"
|
|
type "positive"
|
|
value "buttonNb"
|
|
)
|
|
(GiElement
|
|
name "ledNb"
|
|
type "positive"
|
|
value "ledNb"
|
|
)
|
|
(GiElement
|
|
name "rs232BaudRate"
|
|
type "positive"
|
|
value "rs232Baudrate"
|
|
)
|
|
]
|
|
)
|
|
viewicon (ZoomableIcon
|
|
uid 4066,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "49152,49152,49152"
|
|
)
|
|
xt "45250,30250,46750,31750"
|
|
iconName "BlockDiagram.png"
|
|
iconMaskName "BlockDiagram.msk"
|
|
ftype 1
|
|
)
|
|
ordering 1
|
|
viewiconposition 0
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*41 (Wire
|
|
uid 2318,0
|
|
shape (OrthoPolyLine
|
|
uid 2319,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "43000,30000,44250,40000"
|
|
pts [
|
|
"44250,30000"
|
|
"43000,30000"
|
|
"43000,40000"
|
|
]
|
|
)
|
|
start &28
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2322,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2323,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "41250,28600,45350,30000"
|
|
st "reset"
|
|
blo "41250,29800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*42 (Wire
|
|
uid 2326,0
|
|
shape (OrthoPolyLine
|
|
uid 2327,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "41000,28000,44250,40000"
|
|
pts [
|
|
"44250,28000"
|
|
"41000,28000"
|
|
"41000,40000"
|
|
]
|
|
)
|
|
start &27
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2330,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2331,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "41250,26600,45050,28000"
|
|
st "clock"
|
|
blo "41250,27800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*43 (Wire
|
|
uid 3043,0
|
|
shape (OrthoPolyLine
|
|
uid 3044,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,28000,65000,40000"
|
|
pts [
|
|
"61750,28000"
|
|
"65000,28000"
|
|
"65000,40000"
|
|
]
|
|
)
|
|
start &33
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3047,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3048,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63750,26600,68650,28000"
|
|
st "CS1_n"
|
|
blo "63750,27800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &18
|
|
)
|
|
*44 (Wire
|
|
uid 3051,0
|
|
shape (OrthoPolyLine
|
|
uid 3052,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,26000,67000,40000"
|
|
pts [
|
|
"61750,26000"
|
|
"67000,26000"
|
|
"67000,40000"
|
|
]
|
|
)
|
|
start &34
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3055,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3056,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63750,24600,68450,26000"
|
|
st "RST_n"
|
|
blo "63750,25800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*45 (Wire
|
|
uid 3059,0
|
|
shape (OrthoPolyLine
|
|
uid 3060,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,24000,69000,40000"
|
|
pts [
|
|
"61750,24000"
|
|
"69000,24000"
|
|
"69000,40000"
|
|
]
|
|
)
|
|
start &31
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3063,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3064,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63750,22600,66150,24000"
|
|
st "A0"
|
|
blo "63750,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &20
|
|
)
|
|
*46 (Wire
|
|
uid 3067,0
|
|
shape (OrthoPolyLine
|
|
uid 3068,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,22000,71000,40000"
|
|
pts [
|
|
"61750,22000"
|
|
"71000,22000"
|
|
"71000,40000"
|
|
]
|
|
)
|
|
start &30
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3071,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3072,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63750,20600,66950,22000"
|
|
st "SCL"
|
|
blo "63750,21800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &21
|
|
)
|
|
*47 (Wire
|
|
uid 3075,0
|
|
shape (OrthoPolyLine
|
|
uid 3076,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,20000,73000,40000"
|
|
pts [
|
|
"61750,20000"
|
|
"73000,20000"
|
|
"73000,40000"
|
|
]
|
|
)
|
|
start &29
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3079,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3080,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63750,18600,65850,20000"
|
|
st "SI"
|
|
blo "63750,19800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &22
|
|
)
|
|
*48 (Wire
|
|
uid 3708,0
|
|
shape (OrthoPolyLine
|
|
uid 3709,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "37000,16000,44250,40000"
|
|
pts [
|
|
"44250,16000"
|
|
"37000,16000"
|
|
"37000,40000"
|
|
]
|
|
)
|
|
start &32
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3712,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3713,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "37250,14600,42950,16000"
|
|
st "buttons"
|
|
blo "37250,15800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &23
|
|
)
|
|
*49 (Wire
|
|
uid 3716,0
|
|
shape (OrthoPolyLine
|
|
uid 3717,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "61750,16000,77000,40000"
|
|
pts [
|
|
"61750,16000"
|
|
"77000,16000"
|
|
"77000,40000"
|
|
]
|
|
)
|
|
start &35
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3720,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3721,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63750,14600,66550,15900"
|
|
st "leds"
|
|
blo "63750,15600"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &24
|
|
)
|
|
*50 (Wire
|
|
uid 3819,0
|
|
shape (OrthoPolyLine
|
|
uid 3820,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "39000,20000,44250,40000"
|
|
pts [
|
|
"39000,40000"
|
|
"39000,20000"
|
|
"44250,20000"
|
|
]
|
|
)
|
|
start &12
|
|
end &36
|
|
sat 2
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3823,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3824,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "37600,36000,39000,39200"
|
|
st "RxD"
|
|
blo "38800,39200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &25
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 1
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *51 (PackageList
|
|
uid 9,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*52 (Text
|
|
uid 10,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,0,6500,900"
|
|
st "Package List"
|
|
blo "0,700"
|
|
)
|
|
*53 (MLText
|
|
uid 11,0
|
|
va (VaSet
|
|
)
|
|
xt "0,1200,17500,4800"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 12,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*54 (Text
|
|
uid 13,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,0,30000,900"
|
|
st "Compiler Directives"
|
|
blo "20000,700"
|
|
)
|
|
*55 (Text
|
|
uid 14,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,1000,31500,1900"
|
|
st "Pre-module directives:"
|
|
blo "20000,1700"
|
|
)
|
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sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-400,3400,1000"
|
|
st "sig0"
|
|
blo "0,800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-400,4700,1000"
|
|
st "dbus0"
|
|
blo "0,800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineColor "32768,0,0"
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,-200,4700,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "-2950,-1200,15550,0"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1250,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "-50,150,1350,1350"
|
|
st "1"
|
|
blo "-50,1150"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*78 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "14100,20000,24900,21200"
|
|
st "Frame Declarations"
|
|
blo "14100,21000"
|
|
)
|
|
*79 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21200,14100,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "-1800,-1200,9200,0"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1250,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "-50,150,1350,1350"
|
|
st "1"
|
|
blo "-50,1150"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*80 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "14100,20000,24900,21200"
|
|
st "Frame Declarations"
|
|
blo "14100,21000"
|
|
)
|
|
*81 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21200,14100,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6200,6500,7100"
|
|
st "Declarations"
|
|
blo "0,6900"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7100,3000,8000"
|
|
st "Ports:"
|
|
blo "0,7800"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,8000,4500,8900"
|
|
st "Pre User:"
|
|
blo "0,8700"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,8900,40600,14900"
|
|
st "constant clockFrequency: real := 66.0E6;
|
|
constant spiFrequency: real := 20.0E6;
|
|
constant baudRateDivide: positive := integer((clockFrequency/2.0)/spiFrequency + 1.0);
|
|
constant rs232BaudRate: positive := 128*9600;
|
|
constant buttonNb: positive := 4;
|
|
constant ledNb: positive := 8;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,14900,8500,15800"
|
|
st "Diagram Signals:"
|
|
blo "0,15600"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6200,5500,7100"
|
|
st "Post User:"
|
|
blo "0,6900"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,6200,0,6200"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 58,0
|
|
usingSuid 1
|
|
emptyRow *82 (LEmptyRow
|
|
)
|
|
uid 22,0
|
|
optionalChildren [
|
|
*83 (RefLabelRowHdr
|
|
)
|
|
*84 (TitleRowHdr
|
|
)
|
|
*85 (FilterRowHdr
|
|
)
|
|
*86 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*87 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*88 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*89 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*90 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*91 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*92 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*93 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*94 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*95 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 37,0
|
|
)
|
|
)
|
|
uid 2392,0
|
|
)
|
|
*96 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 38,0
|
|
)
|
|
)
|
|
uid 2394,0
|
|
)
|
|
*97 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "CS1_n"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 47,0
|
|
)
|
|
)
|
|
uid 3081,0
|
|
)
|
|
*98 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "RST_n"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 48,0
|
|
)
|
|
)
|
|
uid 3083,0
|
|
)
|
|
*99 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "A0"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 49,0
|
|
)
|
|
)
|
|
uid 3085,0
|
|
)
|
|
*100 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "SCL"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 50,0
|
|
)
|
|
)
|
|
uid 3087,0
|
|
)
|
|
*101 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "SI"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 51,0
|
|
)
|
|
)
|
|
uid 3089,0
|
|
)
|
|
*102 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "buttons"
|
|
t "std_ulogic_vector"
|
|
b "(1 to buttonNb)"
|
|
o 7
|
|
suid 56,0
|
|
)
|
|
)
|
|
uid 3722,0
|
|
)
|
|
*103 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "leds"
|
|
t "std_ulogic_vector"
|
|
b "(1 to ledNb)"
|
|
o 9
|
|
suid 57,0
|
|
)
|
|
)
|
|
uid 3724,0
|
|
)
|
|
*104 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "RxD"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 58,0
|
|
)
|
|
)
|
|
uid 3825,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 35,0
|
|
optionalChildren [
|
|
*105 (Sheet
|
|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *106 (MRCItem
|
|
litem &82
|
|
pos 10
|
|
dimension 20
|
|
)
|
|
uid 37,0
|
|
optionalChildren [
|
|
*107 (MRCItem
|
|
litem &83
|
|
pos 0
|
|
dimension 20
|
|
uid 38,0
|
|
)
|
|
*108 (MRCItem
|
|
litem &84
|
|
pos 1
|
|
dimension 23
|
|
uid 39,0
|
|
)
|
|
*109 (MRCItem
|
|
litem &85
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 40,0
|
|
)
|
|
*110 (MRCItem
|
|
litem &95
|
|
pos 0
|
|
dimension 20
|
|
uid 2393,0
|
|
)
|
|
*111 (MRCItem
|
|
litem &96
|
|
pos 1
|
|
dimension 20
|
|
uid 2395,0
|
|
)
|
|
*112 (MRCItem
|
|
litem &97
|
|
pos 2
|
|
dimension 20
|
|
uid 3082,0
|
|
)
|
|
*113 (MRCItem
|
|
litem &98
|
|
pos 3
|
|
dimension 20
|
|
uid 3084,0
|
|
)
|
|
*114 (MRCItem
|
|
litem &99
|
|
pos 4
|
|
dimension 20
|
|
uid 3086,0
|
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)
|
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*115 (MRCItem
|
|
litem &100
|
|
pos 5
|
|
dimension 20
|
|
uid 3088,0
|
|
)
|
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*116 (MRCItem
|
|
litem &101
|
|
pos 6
|
|
dimension 20
|
|
uid 3090,0
|
|
)
|
|
*117 (MRCItem
|
|
litem &102
|
|
pos 7
|
|
dimension 20
|
|
uid 3723,0
|
|
)
|
|
*118 (MRCItem
|
|
litem &103
|
|
pos 8
|
|
dimension 20
|
|
uid 3725,0
|
|
)
|
|
*119 (MRCItem
|
|
litem &104
|
|
pos 9
|
|
dimension 20
|
|
uid 3826,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
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|
propVa (MVa
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|
cellColor "0,49152,49152"
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|
fontColor "0,0,0"
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font "Tahoma,10,0"
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|
textAngle 90
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)
|
|
uid 41,0
|
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optionalChildren [
|
|
*120 (MRCItem
|
|
litem &86
|
|
pos 0
|
|
dimension 20
|
|
uid 42,0
|
|
)
|
|
*121 (MRCItem
|
|
litem &88
|
|
pos 1
|
|
dimension 50
|
|
uid 43,0
|
|
)
|
|
*122 (MRCItem
|
|
litem &89
|
|
pos 2
|
|
dimension 100
|
|
uid 44,0
|
|
)
|
|
*123 (MRCItem
|
|
litem &90
|
|
pos 3
|
|
dimension 50
|
|
uid 45,0
|
|
)
|
|
*124 (MRCItem
|
|
litem &91
|
|
pos 4
|
|
dimension 100
|
|
uid 46,0
|
|
)
|
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*125 (MRCItem
|
|
litem &92
|
|
pos 5
|
|
dimension 100
|
|
uid 47,0
|
|
)
|
|
*126 (MRCItem
|
|
litem &93
|
|
pos 6
|
|
dimension 50
|
|
uid 48,0
|
|
)
|
|
*127 (MRCItem
|
|
litem &94
|
|
pos 7
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dimension 80
|
|
uid 49,0
|
|
)
|
|
]
|
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)
|
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fixedCol 4
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|
fixedRow 2
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|
name "Ports"
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|
uid 36,0
|
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vaOverrides [
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|
]
|
|
)
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|
]
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)
|
|
uid 21,0
|
|
)
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|
genericsCommonDM (CommonDM
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|
ldm (LogicalDM
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|
emptyRow *128 (LEmptyRow
|
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)
|
|
uid 51,0
|
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optionalChildren [
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*129 (RefLabelRowHdr
|
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)
|
|
*130 (TitleRowHdr
|
|
)
|
|
*131 (FilterRowHdr
|
|
)
|
|
*132 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*133 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*134 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*135 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*136 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*137 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*138 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*139 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
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|
editShortBounds 1
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uid 63,0
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optionalChildren [
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*140 (Sheet
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|
sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
|
|
)
|
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cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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|
)
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emptyMRCItem *141 (MRCItem
|
|
litem &128
|
|
pos 0
|
|
dimension 20
|
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)
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|
uid 65,0
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optionalChildren [
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*142 (MRCItem
|
|
litem &129
|
|
pos 0
|
|
dimension 20
|
|
uid 66,0
|
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)
|
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*143 (MRCItem
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|
litem &130
|
|
pos 1
|
|
dimension 23
|
|
uid 67,0
|
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)
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|
*144 (MRCItem
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litem &131
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|
pos 2
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|
hidden 1
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|
dimension 20
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|
uid 68,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 69,0
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optionalChildren [
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*145 (MRCItem
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litem &132
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|
pos 0
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|
dimension 20
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uid 70,0
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)
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*146 (MRCItem
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litem &134
|
|
pos 1
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|
dimension 50
|
|
uid 71,0
|
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)
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*147 (MRCItem
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litem &135
|
|
pos 2
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|
dimension 100
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|
uid 72,0
|
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)
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|
*148 (MRCItem
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|
litem &136
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|
pos 3
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|
dimension 100
|
|
uid 73,0
|
|
)
|
|
*149 (MRCItem
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|
litem &137
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|
pos 4
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|
dimension 50
|
|
uid 74,0
|
|
)
|
|
*150 (MRCItem
|
|
litem &138
|
|
pos 5
|
|
dimension 50
|
|
uid 75,0
|
|
)
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|
*151 (MRCItem
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|
litem &139
|
|
pos 6
|
|
dimension 80
|
|
uid 76,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
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|
uid 64,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
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)
|
|
uid 50,0
|
|
type 1
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|
)
|
|
activeModelName "BlockDiag"
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)
|