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30 lines
857 B
VHDL
30 lines
857 B
VHDL
--
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-- VHDL Architecture Cursor_test.pulseWidthModulator_tester.arch_name
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--
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-- Created:
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-- by - Simon.UNKNOWN (PC-SDM)
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-- at - 08:54:14 14.01.2022
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--
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-- using Mentor Graphics HDL Designer(TM) 2019.2 (Build 5)
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--
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ARCHITECTURE arch_name OF pulseWidthModulator_tester IS
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constant clockFrequency: real := 66.0E6;
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constant clockPeriod: time := 1.0/clockFrequency * 1 sec;
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signal clock_int: std_ulogic := '0';
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BEGIN
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-----------------------------------------------------------------------------
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-- clock and reset
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reset <= '1', '0' after 4*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after 9*clockPeriod/10;
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------------------------------------------------------------------------------
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END ARCHITECTURE arch_name;
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