mirror of
https://github.com/Klagarge/Cursor.git
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1723 lines
22 KiB
Plaintext
1723 lines
22 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 2006,0
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|
usingSuid 1
|
|
emptyRow *1 (LEmptyRow
|
|
)
|
|
uid 205,0
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optionalChildren [
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|
*2 (LogPort
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port (LogicalPort
|
|
m 1
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|
decl (Decl
|
|
n "muxOut"
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t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
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o 3
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suid 2,0
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)
|
|
)
|
|
uid 206,0
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|
)
|
|
*3 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in1"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 4
|
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suid 4,0
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|
)
|
|
)
|
|
uid 207,0
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|
)
|
|
*4 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in0"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
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|
o 1
|
|
suid 1,0
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)
|
|
)
|
|
uid 208,0
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|
)
|
|
*5 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "sel"
|
|
t "unsigned"
|
|
b "(1 DOWNTO 0)"
|
|
o 2
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 209,0
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|
)
|
|
*6 (RefLabelRowHdr
|
|
)
|
|
*7 (TitleRowHdr
|
|
)
|
|
*8 (FilterRowHdr
|
|
)
|
|
*9 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*10 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*11 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*12 (NameColHdr
|
|
tm "NameColHdrMgr"
|
|
)
|
|
*13 (ModeColHdr
|
|
tm "ModeColHdrMgr"
|
|
)
|
|
*14 (TypeColHdr
|
|
tm "TypeColHdrMgr"
|
|
)
|
|
*15 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
|
|
)
|
|
*16 (InitColHdr
|
|
tm "InitColHdrMgr"
|
|
)
|
|
*17 (EolColHdr
|
|
tm "EolColHdrMgr"
|
|
)
|
|
*18 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in2"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 2005,0
|
|
)
|
|
)
|
|
uid 302,0
|
|
)
|
|
*19 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in3"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 2006,0
|
|
)
|
|
)
|
|
uid 304,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 210,0
|
|
optionalChildren [
|
|
*20 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
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|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
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|
)
|
|
emptyMRCItem *21 (MRCItem
|
|
litem &1
|
|
pos 6
|
|
dimension 20
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)
|
|
uid 145,0
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|
optionalChildren [
|
|
*22 (MRCItem
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|
litem &6
|
|
pos 0
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|
dimension 20
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|
uid 148,0
|
|
)
|
|
*23 (MRCItem
|
|
litem &7
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|
pos 1
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|
dimension 23
|
|
uid 150,0
|
|
)
|
|
*24 (MRCItem
|
|
litem &8
|
|
pos 2
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|
hidden 1
|
|
dimension 20
|
|
uid 152,0
|
|
)
|
|
*25 (MRCItem
|
|
litem &2
|
|
pos 2
|
|
dimension 20
|
|
uid 171,0
|
|
)
|
|
*26 (MRCItem
|
|
litem &3
|
|
pos 3
|
|
dimension 20
|
|
uid 172,0
|
|
)
|
|
*27 (MRCItem
|
|
litem &4
|
|
pos 0
|
|
dimension 20
|
|
uid 173,0
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|
)
|
|
*28 (MRCItem
|
|
litem &5
|
|
pos 1
|
|
dimension 20
|
|
uid 174,0
|
|
)
|
|
*29 (MRCItem
|
|
litem &18
|
|
pos 4
|
|
dimension 20
|
|
uid 303,0
|
|
)
|
|
*30 (MRCItem
|
|
litem &19
|
|
pos 5
|
|
dimension 20
|
|
uid 305,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 146,0
|
|
optionalChildren [
|
|
*31 (MRCItem
|
|
litem &9
|
|
pos 0
|
|
dimension 20
|
|
uid 154,0
|
|
)
|
|
*32 (MRCItem
|
|
litem &11
|
|
pos 1
|
|
dimension 50
|
|
uid 158,0
|
|
)
|
|
*33 (MRCItem
|
|
litem &12
|
|
pos 2
|
|
dimension 100
|
|
uid 160,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &13
|
|
pos 3
|
|
dimension 50
|
|
uid 162,0
|
|
)
|
|
*35 (MRCItem
|
|
litem &14
|
|
pos 4
|
|
dimension 100
|
|
uid 164,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &15
|
|
pos 5
|
|
dimension 100
|
|
uid 166,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &16
|
|
pos 6
|
|
dimension 50
|
|
uid 168,0
|
|
)
|
|
*38 (MRCItem
|
|
litem &17
|
|
pos 7
|
|
dimension 80
|
|
uid 170,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 144,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 204,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *39 (LEmptyRow
|
|
)
|
|
uid 212,0
|
|
optionalChildren [
|
|
*40 (RefLabelRowHdr
|
|
)
|
|
*41 (TitleRowHdr
|
|
)
|
|
*42 (FilterRowHdr
|
|
)
|
|
*43 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*44 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*45 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*46 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*47 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*48 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*49 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*50 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*51 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 200,0
|
|
)
|
|
*52 (LogGeneric
|
|
generic (GiElement
|
|
name "delay"
|
|
type "time"
|
|
value "gateDelay"
|
|
)
|
|
uid 201,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 213,0
|
|
optionalChildren [
|
|
*53 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *54 (MRCItem
|
|
litem &39
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 176,0
|
|
optionalChildren [
|
|
*55 (MRCItem
|
|
litem &40
|
|
pos 0
|
|
dimension 20
|
|
uid 179,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &41
|
|
pos 1
|
|
dimension 23
|
|
uid 181,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &42
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 183,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &51
|
|
pos 0
|
|
dimension 20
|
|
uid 202,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &52
|
|
pos 1
|
|
dimension 20
|
|
uid 203,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 177,0
|
|
optionalChildren [
|
|
*60 (MRCItem
|
|
litem &43
|
|
pos 0
|
|
dimension 20
|
|
uid 185,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &45
|
|
pos 1
|
|
dimension 50
|
|
uid 189,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &46
|
|
pos 2
|
|
dimension 100
|
|
uid 191,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &47
|
|
pos 3
|
|
dimension 100
|
|
uid 193,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &48
|
|
pos 4
|
|
dimension 50
|
|
uid 195,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &49
|
|
pos 5
|
|
dimension 50
|
|
uid 197,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &50
|
|
pos 6
|
|
dimension 80
|
|
uid 199,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 175,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 211,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\mux4to1@u@logic@vector\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\mux4to1@u@logic@vector\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\mux4to1@u@logic@vector"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\mux4to1ULogicVector"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "mux4to1ULogicVector"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:35:11"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "gates"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/ElN/Libraries/Gates/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "09"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "mux4to1ULogicVector"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Sep"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "September"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\mux4to1@u@logic@vector\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\mux4to1ULogicVector\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelPath"
|
|
value "$ACTEL_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelProjectPath"
|
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ACTEL_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\Board\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:35:11"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "mux4to1ULogicVector"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
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(vvPair
|
|
variable "yy"
|
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value "19"
|
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