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			5 lines
		
	
	
		
			63 B
		
	
	
	
		
			VHDL
		
	
	
	
	
	
			
		
		
	
	
			5 lines
		
	
	
		
			63 B
		
	
	
	
		
			VHDL
		
	
	
	
	
	
| ARCHITECTURE sim OF logic1 IS
 | |
| BEGIN
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|   logic_1 <= '1';
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| END sim;
 |