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106 lines
4.6 KiB
VHDL
106 lines
4.6 KiB
VHDL
library Common;
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use Common.CommonLib.all;
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ARCHITECTURE RTL OF lcdInitializer IS
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constant initializationSequenceLength: positive := 14;
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type initializationDataType is array (1 to initializationSequenceLength+1)
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of std_ulogic_vector(lcdData'range);
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constant initializationData: initializationDataType :=(
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'0' & X"40", -- Display start line 0
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'0' & X"A1", -- ADC reverse
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'0' & X"C0", -- Normal COM0~COM31
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'0' & X"A6", -- Display normal
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'0' & X"A2", -- Set bias 1/9 (Duty 1/33)
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'0' & X"2F", -- Booster, Regulator and Follower on
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'0' & X"F8", -- Set internal Booster to 3x / 4x
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'0' & X"00", --
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'0' & X"23", -- Contrast set
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'0' & X"81", --
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'0' & X"1F", --
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'0' & X"AC", -- No indicator
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'0' & X"00", --
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'0' & X"AF", -- Display on
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std_ulogic_vector(to_unsigned(0, lcdData'length))
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);
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constant clearDisplaySequenceLength : positive := 566;--(3+132)*4 + 3; -- (3 commands + 132 columns) * 4 pages + jump back to start
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constant clearDisplayDataLength : positive := 6;
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type clearDisplayDataType is array (1 to clearDisplayDataLength+1)
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of std_ulogic_vector(lcdData'range);
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constant clearDisplayData: clearDisplayDataType :=(
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-- ind seq
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'0' & X"B0", -- 1 Page 0
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'0' & X"B1", -- 2 Page 1
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'0' & X"B2", -- 3 Page 2
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'0' & X"B3", -- 4 Page 3
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'0' & X"10", -- 5 Column MSB 0
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'0' & X"00", -- 6 Column LSB 0
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'1' & X"00" -- 7 Data "empty"
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);
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signal initSequenceCounter: unsigned(requiredBitNb(initializationSequenceLength+1)-1 downto 0);
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signal initSequenceDone: std_ulogic;
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signal clearSequenceCounter: unsigned(requiredBitNb(clearDisplaySequenceLength+1)-1 downto 0);
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signal clearSequenceDone: std_ulogic;
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BEGIN
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------------------------------------------------------------------------------
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-- initialization sequence counter
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buildInitSequence: process(reset, clock)
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begin
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if reset='1' then
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initSequenceCounter <= to_unsigned(1, initSequenceCounter'length);
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elsif rising_edge(clock) then
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if lcdBusy = '0' then
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if initSequenceDone = '0' then
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initSequenceCounter <= initSequenceCounter + 1;
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end if;
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end if;
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end if;
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end process buildInitSequence;
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initSequenceDone <= '1' when initSequenceCounter > initializationSequenceLength
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else '0';
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------------------------------------------------------------------------------
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-- clear sequence counter
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buildClearSequence: process(reset, clock)
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begin
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if reset='1' then
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clearSequenceCounter <= to_unsigned(clearDisplaySequenceLength+1, clearSequenceCounter'length);
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elsif rising_edge(clock) then
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if lcdBusy = '0' then
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if clearDisplay = '1' and initSequenceDone = '1' then
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clearSequenceCounter <= to_unsigned(1, clearSequenceCounter'length);
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elsif clearSequenceDone = '0' then
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clearSequenceCounter <= clearSequenceCounter + 1;
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end if;
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end if;
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end if;
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end process buildClearSequence;
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clearSequenceDone <= '1' when clearSequenceCounter > clearDisplaySequenceLength
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else '0';
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------------------------------------------------------------------------------
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-- data multiplexer
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lcdData <= columnData when (initSequenceDone = '1' and clearSequenceDone = '1')
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else initializationData(to_integer(initSequenceCounter)) when (initSequenceCounter > 0 and initSequenceDone = '0')
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else clearDisplayData(1) when (clearSequenceCounter = 1 or clearSequenceCounter = 564)
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else clearDisplayData(2) when (clearSequenceCounter = 137)
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else clearDisplayData(3) when (clearSequenceCounter = 273)
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else clearDisplayData(4) when (clearSequenceCounter = 409)
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else clearDisplayData(5) when (clearSequenceCounter = 2 or clearSequenceCounter = 138 or clearSequenceCounter = 274 or clearSequenceCounter = 410 or clearSequenceCounter = 565)
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else clearDisplayData(6) when (clearSequenceCounter = 3 or clearSequenceCounter = 139 or clearSequenceCounter = 275 or clearSequenceCounter = 411 or clearSequenceCounter = 566)
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else clearDisplayData(7);
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lcdSend <= columnSend when initSequenceDone = '1' and clearSequenceDone = '1'
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else not lcdBusy when initSequenceCounter <= initializationSequenceLength
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else not lcdBusy when clearSequenceCounter <= clearDisplaySequenceLength
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else '0';
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columnBusy <= lcdBusy when initSequenceDone = '1' and clearSequenceDone = '1'
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else '1';
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END ARCHITECTURE RTL;
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