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Initial commit
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Rémi Heredero
47
Libs/Lcd_test/hdl/lcdController_tester_test.vhd
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47
Libs/Lcd_test/hdl/lcdController_tester_test.vhd
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ARCHITECTURE test OF lcdController_tester IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_ulogic := '1';
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constant testInterval: time := 5 us;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- send sequence
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process
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begin
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ascii <= (others => '0');
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send <= '0';
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wait until falling_edge(busy);
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wait for testInterval;
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-- send single character
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wait until rising_edge(clock_int);
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ascii <= std_ulogic_vector(to_unsigned(character'pos('a'), ascii'length));
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send <= '1', '0' after clockPeriod;
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wait until rising_edge(busy);
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wait until falling_edge(busy);
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wait for testInterval;
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-- send character stream
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for index in character'pos('b') to character'pos('d') loop
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ascii <= std_ulogic_vector(to_unsigned(index, ascii'length));
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send <= '1', '0' after clockPeriod;
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wait until rising_edge(busy);
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wait until falling_edge(busy);
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wait for 1 ns;
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end loop;
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wait for testInterval;
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-- end of simulation
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assert false
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report "End of simulation"
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severity failure;
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wait;
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end process;
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END ARCHITECTURE test;
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111
Libs/Lcd_test/hdl/lcdDemo_tester_test.vhd
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111
Libs/Lcd_test/hdl/lcdDemo_tester_test.vhd
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ARCHITECTURE test OF lcdDemo_tester IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_ulogic := '1';
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constant testInterval:time := 0.1 ms;
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constant initSequenceLength:time := 20 us;
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constant helloSequenceLength:time := 1 ms;
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constant rs232Frequency: real := real(baudRate);
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constant rs232Period: time := (1.0/rs232Frequency) * 1 sec;
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constant rs232WriteInterval: time := 10*rs232Period;
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signal rs232OutString : string(1 to 32);
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signal rs232SendOutString: std_uLogic;
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signal rs232SendOutDone: std_uLogic;
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signal rs232OutByte: character;
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signal rs232SendOutByte: std_uLogic;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- test sequence
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process
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begin
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rs232SendOutString <= '0';
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buttons <= (others => '0');
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wait for initSequenceLength + helloSequenceLength;
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-- send bytes from serial port
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rs232OutString <= "a ";
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rs232SendOutString <= '1', '0' after 1 ns;
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wait until rs232SendOutDone = '1';
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wait for rs232WriteInterval;
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rs232OutString <= "hello world ";
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rs232SendOutString <= '1', '0' after 1 ns;
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wait until rs232SendOutDone = '1';
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wait for rs232WriteInterval;
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wait for testInterval;
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-- send hello message
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wait until rising_edge(clock_int);
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for index in buttons'range loop
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buttons(index) <= '1';
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wait until rising_edge(clock_int);
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buttons(index) <= '0';
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wait until rising_edge(clock_int);
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end loop;
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wait for helloSequenceLength;
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wait for testInterval;
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-- end of simulation
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assert false
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report "End of simulation"
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severity failure;
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wait;
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end process;
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--============================================================================
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-- RS232 send
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rsSendSerialString: process
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constant rs232BytePeriod : time := 15*rs232Period;
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variable commandRight: natural;
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begin
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rs232SendOutByte <= '0';
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rs232SendOutDone <= '0';
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wait until rising_edge(rs232SendOutString);
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commandRight := rs232OutString'right;
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while rs232OutString(commandRight) = ' ' loop
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commandRight := commandRight-1;
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end loop;
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for index in rs232OutString'left to commandRight loop
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rs232OutByte <= rs232OutString(index);
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rs232SendOutByte <= '1', '0' after 1 ns;
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wait for rs232BytePeriod;
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end loop;
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rs232OutByte <= cr;
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rs232SendOutByte <= '1', '0' after 1 ns;
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wait for rs232BytePeriod;
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rs232SendOutDone <= '1';
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wait for 1 ns;
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end process rsSendSerialString;
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-- send byte
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rsSendSerialByte: process
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variable txData: unsigned(7 downto 0);
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begin
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RxD <= '1';
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wait until rising_edge(rs232SendOutByte);
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txData := to_unsigned(character'pos(rs232OutByte), txData'length);
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RxD <= '0';
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wait for rs232Period;
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for index in txData'reverse_range loop
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RxD <= txData(index);
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wait for rs232Period;
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end loop;
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end process rsSendSerialByte;
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END ARCHITECTURE test;
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69
Libs/Lcd_test/hdl/lcdSerializer_tester_test.vhd
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69
Libs/Lcd_test/hdl/lcdSerializer_tester_test.vhd
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@@ -0,0 +1,69 @@
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ARCHITECTURE test OF lcdSerializer_tester IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_ulogic := '1';
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constant initializationSequenceLength: positive := 14;
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type initializtionDataType is array (1 to initializationSequenceLength)
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of std_ulogic_vector(data'range);
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constant initializtionData: initializtionDataType :=(
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'0' & X"40", -- Display start line 0
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'0' & X"A1", --
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'0' & X"C0", --
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'0' & X"A6", --
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'0' & X"A2", --
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'0' & X"2F", --
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'0' & X"F8", --
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'0' & X"00", --
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'0' & X"23", --
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'0' & X"81", --
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'0' & X"1F", --
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'0' & X"AC", --
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'0' & X"00", --
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'0' & X"AF" --
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);
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- send sequence
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process
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begin
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data <= (others => '0');
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send <= '0';
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wait until falling_edge(busy);
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-- send initialization codes
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wait until rising_edge(clock_int);
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for index in initializtionData'range loop
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data <= initializtionData(index);
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send <= '1', '0' after clockPeriod;
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wait until rising_edge(busy);
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wait until falling_edge(busy);
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wait for 1 ns;
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end loop;
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wait for 100*clockPeriod;
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-- send pixel codes
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wait until rising_edge(clock_int);
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for index in 1 to 8 loop
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data <= std_ulogic_vector(to_unsigned(index, data'length));
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data(data'high) <= '1';
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send <= '1', '0' after clockPeriod;
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wait until rising_edge(busy);
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wait until falling_edge(busy);
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wait for 1 ns;
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end loop;
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wait for 100*clockPeriod;
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-- end of simulation
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assert false
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report "End of simulation"
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severity failure;
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wait;
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end process;
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END ARCHITECTURE test;
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