Klagarge/Cursor
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Rémi Heredero
2021-11-24 10:50:51 +01:00
commit c7ba678fbb
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Libs/IO/hdl/tristateBufferULogicVector_sim.vhd Normal file
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ARCHITECTURE sim OF tristateBufferULogicVector IS
BEGIN
out1 <= std_logic_vector(in1) after delay when OE = '1' else (others => 'Z') after delay;
END ARCHITECTURE sim;