Klagarge/Cursor
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This commit is contained in:
Rémi Heredero
2021-11-24 10:50:51 +01:00
commit c7ba678fbb
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Libs/Gates/hdl/logic0_sim.vhd Normal file
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@@ -0,0 +1,4 @@
ARCHITECTURE sim OF logic0 IS
BEGIN
logic_0 <= '0';
END sim;