Initial commit

Libs/Common/hdl/blinker_arch.vhd

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+-- filename:          blinker.vhd
+-- kind:              vhdl file
+-- first created:     18.06.2012
+-- created by:        zas
+--------------------------------------------------------------------------------
+-- History:
+-- v0.1 : zas 18.06.2012 -- Initial Version
+--------------------------------------------------------------------------------
+-- Description:
+-- For let blinking a LED with an signal event
+-- Mode = 0 (reactive on rising edge)
+--             ___________________________________________
+-- input  ____/
+--             ___________________
+-- output ____/                   \_______________________
+-- time   0s                    0.5s                    1s
+--
+--             _
+-- input  ____/ \_________________________________________
+--             ___________________
+-- output ____/                   \_______________________
+-- time   0s                    0.5s                    1s
+----
+-- Mode = 1 (reactive on falling edge)
+--        _____
+-- input       \__________________________________________
+--               ___________________
+-- output ______/                   \_____________________
+-- time   0s                    0.5s                    1s
+--
+--             _
+-- input  ____/ \_________________________________________
+--                ___________________
+-- output ______ /                   \____________________
+-- time   0s                    0.5s                    1s
+--
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.NUMERIC_STD.all;
+
+LIBRARY Common;
+USE Common.CommonLib.all;
+
+
+ARCHITECTURE arch OF blinker IS
+
+  constant c : integer := clockFrequency/2; -- 500ms blink
+
+  signal cnt       : unsigned(requiredBitNb(c)-1 downto 0);
+  signal en_delay  : std_ulogic;
+  signal blink_int : std_ulogic;
+
+BEGIN
+
+  process(reset, clock)
+  begin
+    if reset = '1' then
+      en_delay  <= '0';
+      blink_int <= '0';
+      cnt       <= (others => '0');
+    elsif rising_edge(clock) then
+      en_delay <= en;
+      -- detect rising_edge
+      if mode = 0 then
+        if blink_int = '0' and en_delay = '0' and en = '1' then
+          blink_int <= '1';
+        end if;
+      else
+      -- detect falling edge
+        if blink_int = '0' and en_delay = '1' and en = '0' then
+          blink_int <= '1';
+        end if;
+      end if;
+      -- blink
+      if blink_int = '1' then
+        if (cnt < c) then
+          cnt <= cnt + 1;
+        else
+          cnt       <= (others => '0');
+          blink_int <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- Set output
+  blink <= blink_int;
+END ARCHITECTURE arch;

Libs/Common/hdl/commonLib.vhd

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+--------------------------------------------------------------------------------
+-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch)
+--------------------------------------------------------------------------------
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program IS distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License along with
+-- this program. If not, see <http://www.gnu.org/licenses/>
+-- -----------------------------------------------------------------------------
+-- Common Lib
+--
+-- -----------------------------------------------------------------------------
+--  Authors:
+--    cof: [Fran<61>ois Corthay](francois.corthay@hevs.ch)
+--    guo: [Oliver A. Gubler](oliver.gubler@hevs.ch)
+-- -----------------------------------------------------------------------------
+-- Changelog:
+--   2016-06 : guo
+--     added function sel
+--   2015-06 : guo
+--     added counterBitNb
+--     added documentation
+-- -----------------------------------------------------------------------------
+library IEEE;
+  use IEEE.std_logic_1164.all;
+  use IEEE.numeric_std.all;
+
+PACKAGE CommonLib IS
+
+  ------------------------------------------------------------------------------
+  -- Returns the number of bits needed to represent the given val
+  -- Examples:
+  --   requiredBitNb(1) = 1   (1)
+  --   requiredBitNb(2) = 2   (10)
+  --   requiredBitNb(3) = 2   (11)
+  function requiredBitNb(val : integer) return integer;
+
+  ------------------------------------------------------------------------------
+  -- Returns the number of bits needed to count val times (0 to val-1)
+  -- Examples:
+  --   counterBitNb(1) = 1    (0)
+  --   counterBitNb(2) = 1    (0->1)
+  --   counterBitNb(3) = 2    (0->1->10)
+  function counterBitNb(val : integer) return integer;
+
+  ------------------------------------------------------------------------------
+  -- Functions to return one or the other input based on a boolean.
+  -- Can be used to build conditional constants.
+  -- Example:
+  --   constant bonjour_c : string := sel(ptpRole = master, "fpga20", "fpga02");
+  function sel(Cond : BOOLEAN; If_True, If_False : integer)
+                                            return integer;
+  function sel(Cond : BOOLEAN; If_True, If_False : string)
+                                            return string;
+  function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector)
+                                            return std_ulogic_vector;
+  function sel(Cond : BOOLEAN; If_True, If_False : unsigned)
+                                            return unsigned;
+  function sel(Cond : BOOLEAN; If_True, If_False : signed)
+                                            return signed;
+
+END CommonLib;

Libs/Common/hdl/commonLib_body.vhd

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+--------------------------------------------------------------------------------
+-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch)
+--------------------------------------------------------------------------------
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program IS distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License along with
+-- this program. If not, see <http://www.gnu.org/licenses/>
+-- -----------------------------------------------------------------------------
+-- Often used functions
+--
+-- -----------------------------------------------------------------------------
+--  Authors:
+--    cof: [Fran<61>ois Corthay](francois.corthay@hevs.ch)
+--    guo: [Oliver A. Gubler](oliver.gubler@hevs.ch)
+-- -----------------------------------------------------------------------------
+-- Changelog:
+--   2016-06 : guo
+--     added function sel
+--   2015-06 : guo
+--     added counterBitNb
+-- -----------------------------------------------------------------------------
+PACKAGE BODY CommonLib IS
+
+  function requiredBitNb (val : integer) return integer is
+    variable powerOfTwo, bitNb : integer;
+  begin
+    powerOfTwo := 1;
+    bitNb := 0;
+    while powerOfTwo <= val loop
+      powerOfTwo := 2 * powerOfTwo;
+      bitNb := bitNb + 1;
+    end loop;
+    return bitNb;
+  end requiredBitNb;
+
+  function counterBitNb (val : integer) return integer is
+    variable powerOfTwo, bitNb : integer;
+  begin
+    powerOfTwo := 1;
+    bitNb := 0;
+    while powerOfTwo < val loop
+      powerOfTwo := 2 * powerOfTwo;
+      bitNb := bitNb + 1;
+    end loop;
+    return bitNb;
+  end counterBitNb;
+
+  function sel(Cond : BOOLEAN; If_True, If_False : integer)
+                                            return integer is
+  begin
+    if (Cond = TRUE) then
+      return (If_True);
+    else
+      return (If_False);
+    end if;
+  end function sel;
+
+  function sel(Cond : BOOLEAN; If_True, If_False : string)
+                                            return string is
+  begin
+    if (Cond = TRUE) then
+      return (If_True);
+    else
+      return (If_False);
+    end if;
+  end function sel;
+
+  function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector)
+                                            return std_ulogic_vector is
+  begin
+    if (Cond = TRUE) then
+      return (If_True);
+    else
+      return (If_False);
+    end if;
+  end function sel;
+
+  function sel(Cond : BOOLEAN; If_True, If_False : unsigned)
+                                            return unsigned is
+  begin
+    if (Cond = TRUE) then
+      return (If_True);
+    else
+      return (If_False);
+    end if;
+  end function sel;
+
+  function sel(Cond : BOOLEAN; If_True, If_False : signed)
+                                            return signed is
+  begin
+    if (Cond = TRUE) then
+      return (If_True);
+    else
+      return (If_False);
+    end if;
+  end function sel;
+
+END CommonLib;

Libs/Common/hdl/debouncerULogicVector_RTL.vhd

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+-- filename:          debouncer.vhd
+-- kind:              vhdl file
+-- first created:     05.03.2012
+-- created by:        zas
+--------------------------------------------------------------------------------
+-- History:
+-- v0.1 : zas 05.03.2012 -- Initial Version
+-- v0.2 : cof 22.01.2013 -- synchronization to clock
+--------------------------------------------------------------------------------
+-- Description: 
+-- Debounces a button on both edges.
+--             _   _   ____________________   _   _
+-- input  ____/ \_/ \_/                    \_/ \_/ \______
+--              _____________________________
+-- output _____/                             \____________
+--
+--------------------------------------------------------------------------------
+
+ARCHITECTURE rtl OF debouncerULogicVector IS
+ 
+  signal inputNormal : std_ulogic_vector(input'range);
+  signal inputSynch, inputDelayed, inputChanged : std_ulogic;
+  signal debounceCounter : unsigned(counterBitNb-1 downto 0);
+ 
+BEGIN
+  ------------------------------------------------------------------------------
+                                                               -- adapt polarity
+  adaptPolarity: process(input)
+  begin
+    for index in input'range loop
+      inputNormal(index) <= input(index) xor invertInput;
+    end loop;
+  end process adaptPolarity;
+
+  ------------------------------------------------------------------------------
+                                                   -- Synchronize input to clock
+  synchInput: process(reset, clock)
+    variable inputOr : std_ulogic;
+  begin
+    if reset = '1' then
+      inputSynch <= '0';
+    elsif rising_edge(clock) then
+      inputOr := '0';
+      for index in input'range loop
+        inputOr := inputOr or inputNormal(index);
+      end loop;
+      inputSynch <= inputOr;
+    end if;
+  end process synchInput;
+
+  ------------------------------------------------------------------------------
+                                                           -- Find edge on input
+  delayInput: process(reset, clock)
+  begin
+    if reset = '1' then
+      inputDelayed <= '0';
+    elsif rising_edge(clock) then
+      inputDelayed <= inputSynch;
+    end if;
+  end process delayInput;
+
+  inputChanged <= '1' when inputDelayed /= inputSynch
+    else '0';
+
+  ------------------------------------------------------------------------------
+                                                             -- Debounce counter
+  countDeadTime: process(reset, clock)
+  begin
+    if reset = '1' then
+      debounceCounter <= (others => '0');
+    elsif rising_edge(clock) then
+      if debounceCounter = 0 then
+        if inputChanged = '1' then
+          debounceCounter <= debounceCounter - 1;
+        end if;
+      else
+        debounceCounter <= debounceCounter - 1;
+      end if;
+    end if;
+  end process countDeadTime;
+
+  ------------------------------------------------------------------------------
+                                                                -- Update output
+  updateOutput: process(reset, clock)
+  begin
+    if reset = '1' then
+      debounced <= (others => '0');
+    elsif rising_edge(clock) then
+      if (inputChanged = '1') and (debounceCounter = 0) then
+        debounced <= inputNormal;
+      elsif debounceCounter = 1 then
+        debounced <= inputNormal;
+      end if;
+    end if;
+  end process updateOutput;
+ 
+END ARCHITECTURE rtl;

Libs/Common/hdl/debouncer_RTL.vhd

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+-- filename:          debouncer.vhd
+-- kind:              vhdl file
+-- first created:     05.03.2012
+-- created by:        zas
+--------------------------------------------------------------------------------
+-- History:
+-- v0.1 : zas 05.03.2012 -- Initial Version
+-- v0.2 : cof 22.01.2013 -- synchronization to clock
+--                       -- direct reaction on both edges
+--------------------------------------------------------------------------------
+-- Description: 
+-- Debounces a button on both edges.
+--             _   _   ____________________   _   _
+-- input  ____/ \_/ \_/                    \_/ \_/ \______
+--              _____________________________
+-- output _____/                             \____________
+--
+--------------------------------------------------------------------------------
+
+ARCHITECTURE rtl OF debouncer IS
+ 
+  signal debounceCounter : unsigned(counterBitNb-1 downto 0);
+  signal inputSynch, inputDelayed, inputChanged : std_ulogic;
+ 
+BEGIN
+  ------------------------------------------------------------------------------
+                                                   -- Synchronize input to clock
+  synchInput: process(reset, clock)
+  begin
+    if reset = '1' then
+      inputSynch <= '0';
+    elsif rising_edge(clock) then
+      inputSynch <= input xor invertInput;
+    end if;
+  end process synchInput;
+
+  ------------------------------------------------------------------------------
+                                                           -- Find edge on input
+  delayInput: process(reset, clock)
+  begin
+    if reset = '1' then
+      inputDelayed <= '0';
+    elsif rising_edge(clock) then
+      inputDelayed <= inputSynch;
+    end if;
+  end process delayInput;
+
+  inputChanged <= '1' when inputDelayed /= inputSynch
+    else '0';
+
+  ------------------------------------------------------------------------------
+                                                             -- Debounce counter
+  countDeadTime: process(reset, clock)
+  begin
+    if reset = '1' then
+      debounceCounter <= (others => '0');
+    elsif rising_edge(clock) then
+      if debounceCounter = 0 then
+        if inputChanged = '1' then
+          debounceCounter <= debounceCounter - 1;
+        end if;
+      else
+        debounceCounter <= debounceCounter - 1;
+      end if;
+    end if;
+  end process countDeadTime;
+
+  ------------------------------------------------------------------------------
+                                                                -- Update output
+  updateOutput: process(reset, clock)
+  begin
+    if reset = '1' then
+      debounced <= '0';
+    elsif rising_edge(clock) then
+      if (inputChanged = '1') and (debounceCounter = 0) then
+        debounced <= input;
+      elsif debounceCounter = 1 then
+        debounced <= input;
+      end if;
+    end if;
+  end process updateOutput;
+ 
+END ARCHITECTURE rtl;

Libs/Common/hdl/edgeDetector_rtl.vhd

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+--------------------------------------------------------------------------------
+-- Copyright 2014 HES-SO Valais Wallis (www.hevs.ch)
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program IS distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License along with
+-- this program. If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+-- EdgeDetector
+--   Detect rising and falling edges of a signal.
+--
+--------------------------------------------------------------------------------
+-- History:
+-- v0.1 : guo 2014-04-02 -- Initial version
+-- v1.0 : cof 2019-10-02 -- Updated symbol
+--------------------------------------------------------------------------------
+ARCHITECTURE RTL OF edgeDetector IS
+  
+  SIGNAL pulse_delayed : std_ulogic;
+  SIGNAL rising_detected_s : std_ulogic;
+  SIGNAL falling_detected_s : std_ulogic;
+
+BEGIN
+
+  -- delay pulse
+  reg : PROCESS (reset, clock)
+  BEGIN
+    IF reset = '1' THEN
+      pulse_delayed <= '0';
+    ELSIF rising_edge(clock) THEN
+      pulse_delayed <= pulse;  
+    END IF;    
+  END PROCESS reg ;
+  
+  -- edge detection
+  rising <= '1' when (pulse = '1') and (pulse_delayed = '0')
+    else '0'; 
+  falling <= '1' when (pulse = '0') and (pulse_delayed = '1')
+    else '0'; 
+  
+END ARCHITECTURE RTL;

Libs/Common/hdl/rotaryToUnsigned_rtl.vhd

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+ARCHITECTURE rtl OF rotaryToUnsigned IS
+
+  signal rotaryDelayed1, rotaryDelayed2, rotaryStable : unsigned(rotary'range);
+  signal rotary_changed : std_ulogic;
+  signal glitchDelayCounter : unsigned(counterBitNb-1 downto 0);
+  signal rotaryStableDelayed : unsigned(rotary'range);
+  signal numberMsbs : unsigned(number'length-rotary'length-1 downto 0);
+
+BEGIN
+  ------------------------------------------------------------------------------
+                                         -- synchronize input and detect changes
+  delayRotary: process(reset, clock)
+  begin
+    if reset = '1' then
+      rotaryDelayed1 <= (others => '0');
+      rotaryDelayed2 <= (others => '0');
+    elsif rising_edge(clock) then
+      rotaryDelayed1 <= rotary;
+      rotaryDelayed2 <= rotaryDelayed1;
+    end if;
+  end process delayRotary;
+
+  rotary_changed <= '1' when rotaryDelayed1 /= rotaryDelayed2
+    else '0';
+                                                              -- count dead time
+  countDeadTime: process(reset, clock)
+  begin
+    if reset = '1' then
+      glitchDelayCounter <= (others => '1');
+    elsif rising_edge(clock) then
+      if rotary_changed = '1' then
+        glitchDelayCounter <= (others => '1');
+      elsif glitchDelayCounter > 0 then
+        glitchDelayCounter <= glitchDelayCounter - 1;
+      end if;
+    end if;
+  end process countDeadTime;
+                                                -- store new rotary button value
+  storeRotary: process(reset, clock)
+  begin
+    if reset = '1' then
+      rotaryStable <= (others => '0');
+    elsif rising_edge(clock) then
+      if glitchDelayCounter = 0 then
+        rotaryStable <= rotaryDelayed2;
+      end if;
+    end if;
+  end process storeRotary;
+
+  ------------------------------------------------------------------------------
+                                     -- keep previous value of stablilzed rotary
+  delayRotaryStable: process(reset, clock)
+  begin
+    if reset = '1' then
+      rotaryStableDelayed <= (others => '0');
+    elsif rising_edge(clock) then
+      rotaryStableDelayed <= rotaryStable;
+    end if;
+  end process delayRotaryStable;
+                                         -- synchronize input and detect changes
+  updateMsbs: process(reset, clock)
+  begin
+    if reset = '1' then
+      numberMsbs <= (others => '0');
+    elsif rising_edge(clock) then
+      if (rotaryStable = 0) and (rotaryStableDelayed+1 = 0) then
+        numberMsbs <= numberMsbs + 1;
+      elsif (rotaryStable+1 = 0) and (rotaryStableDelayed = 0) then
+        numberMsbs <= numberMsbs - 1;
+      end if;
+    end if;
+  end process updateMsbs;
+
+  number <= numberMsbs & rotaryStableDelayed;
+
+END ARCHITECTURE rtl;

Libs/Common/hdl/spikeFilter_RTL.vhd

@@ -0,0 +1,82 @@
+--------------------------------------------------------------------------------
+-- Description: 
+-- Filters short time spikes.
+--             _   _   ____________________   _   _
+-- input  ____/ \_/ \_/                    \_/ \_/ \_________________
+--                         _____________________________
+-- output ________________/                             \____________
+--
+--------------------------------------------------------------------------------
+
+ARCHITECTURE rtl OF spikeFilter IS
+ 
+  signal filterCounter : unsigned(counterBitNb-1 downto 0);
+  signal inputSynch, inputDelayed, inputChanged : std_ulogic;
+ 
+BEGIN
+  ------------------------------------------------------------------------------
+                                                   -- Synchronize input to clock
+  synchInput: process(reset, clock)
+  begin
+    if reset = '1' then
+      inputSynch <= '0';
+    elsif rising_edge(clock) then
+      inputSynch <= input xor invertInput;
+    end if;
+  end process synchInput;
+
+  ------------------------------------------------------------------------------
+                                                           -- Find edge on input
+  delayInput: process(reset, clock)
+  begin
+    if reset = '1' then
+      inputDelayed <= '0';
+    elsif rising_edge(clock) then
+      inputDelayed <= inputSynch;
+    end if;
+  end process delayInput;
+
+  inputChanged <= '1' when inputDelayed /= inputSynch
+    else '0';
+
+  ------------------------------------------------------------------------------
+                                                             -- Debounce counter
+  countDeadTime: process(reset, clock)
+  begin
+    if reset = '1' then
+      filterCounter <= (others => '0');
+    elsif rising_edge(clock) then
+      if filterCounter = 0 then
+        if inputChanged = '1' then
+          filterCounter <= filterCounter + 1;
+        end if;
+      elsif signed(filterCounter)+1 = 0 then
+        if inputChanged = '1' then
+          filterCounter <= filterCounter - 1;
+        end if;
+      else
+        if inputSynch = '0' then
+          filterCounter <= filterCounter - 1;
+        else
+          filterCounter <= filterCounter + 1;
+        end if;
+      end if;
+    end if;
+  end process countDeadTime;
+
+  ------------------------------------------------------------------------------
+                                                                -- Update output
+  updateOutput: process(reset, clock)
+  begin
+    if reset = '1' then
+      filtered <= '0';
+    elsif rising_edge(clock) then
+      if filterCounter = 0 then
+        filtered <= '0';
+      elsif signed(filterCounter)+1 = 0 then
+        filtered <= '1';
+      end if;
+    end if;
+  end process updateOutput;
+ 
+END ARCHITECTURE rtl;

Libs/Common/hdl/toggler_RTL.vhd

@@ -0,0 +1,90 @@
+-- filename:          toggler.vhd
+-- kind:              vhdl file
+-- first created:     05.03.2012
+-- created by:        zas
+--------------------------------------------------------------------------------
+-- History:
+-- v0.1 : cof 22.01.2013 -- Initial version
+--------------------------------------------------------------------------------
+-- Description: 
+-- Debounces a button on both edges.
+--             _                            _
+-- input  ____/ \__________________________/ \____________
+--              _____________________________
+-- output _____/                             \____________
+--
+-- If the generic "counterBitNb" is greater than zero, a debouncer is placed on
+-- the input signal.
+--
+--------------------------------------------------------------------------------
+
+ARCHITECTURE rtl OF toggler IS
+ 
+  signal inputDebounced : std_ulogic;
+  signal inputDelayed, inputChangedTo1 : std_ulogic;
+  signal toggle_int : std_ulogic;
+
+  COMPONENT debouncer
+  GENERIC (
+    counterBitNb : positive := 18;
+    invertInput : std_ulogic := '0'
+  );
+  PORT (
+    reset     : IN     std_ulogic ;
+    clock     : IN     std_ulogic ;
+    input     : IN     std_ulogic ;
+    debounced : OUT    std_ulogic 
+  );
+  END COMPONENT;
+
+BEGIN
+  ------------------------------------------------------------------------------
+                                                               -- Debounce input
+  useInputDirectly: if counterBitNb = 0 generate
+    inputDebounced <= input;
+  end generate useInputDirectly;
+
+  debounceInput: if counterBitNb > 0 generate
+    I_debouncer : debouncer
+      GENERIC MAP (
+        counterBitNb => counterBitNb,
+        invertInput => invertInput
+      )
+      PORT MAP (
+        reset     => reset,
+        clock     => clock,
+        input     => input,
+        debounced => inputDebounced
+      );
+  end generate debounceInput;
+
+  ------------------------------------------------------------------------------
+                                                           -- Find edge on input
+  delayInput: process(reset, clock)
+  begin
+    if reset = '1' then
+      inputDelayed <= '0';
+    elsif rising_edge(clock) then
+      inputDelayed <= inputDebounced;
+    end if;
+  end process delayInput;
+
+  inputChangedTo1 <= '1' when (inputDebounced = '1') and (inputDelayed = '0')
+    else '0';
+
+  ------------------------------------------------------------------------------
+                                                                -- Toggle output
+  toggleOutput: process(reset, clock)
+  begin
+    if reset = '1' then
+      toggle_int <= '0';
+    elsif rising_edge(clock) then
+      if inputChangedTo1 = '1' then
+        toggle_int <= not toggle_int;
+      end if;
+    end if;
+  end process toggleOutput;
+ 
+   toggle <= toggle_int;
+ 
+END ARCHITECTURE rtl;