435 lines
10 KiB
Typst
435 lines
10 KiB
Typst
#import "@preview/cetz:0.2.2": draw
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#import "../src/lib.typ": *
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#set page(flipped: true, paper: "a3")
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#circuit({
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element.multiplexer(
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x: 0, y: 0, w: .5, h: 1.5, id: "PCMux",
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entries: 2,
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fill: util.colors.blue,
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h-ratio: 80%
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)
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element.block(
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x: (rel: 2, to: "PCMux.east"),
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y: (from: "PCMux-port-out", to: "in"),
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w: 1, h: 1.5, id: "PCBuf",
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ports: (
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north: ((id: "clk", clock: true),),
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west: ((id: "in"),),
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east: ((id: "out"),)
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),
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fill: util.colors.green
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)
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element.block(
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x: (rel: 2, to: "PCBuf.east"),
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y: (from: "PCBuf-port-out", to: "A"),
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w: 3, h: 4, id: "IMem",
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ports: (
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west: (
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(id: "A", name: "A"),
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),
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east: (
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(id: "RD", name: "RD"),
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)
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),
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ports-margins: (
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west: (0%, 50%),
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east: (0%, 50%)
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),
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fill: util.colors.green,
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name: "Instruction\nMemory"
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)
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element.block(
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x: (rel: 3, to: "IMem.east"),
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y: (from: "IMem-port-RD", to: "A1"),
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w: 4.5, h: 4, id: "RegFile",
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ports: (
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north: (
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(id: "clk", clock: true, small: true),
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(id: "WE3", name: "WE3"),
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(id: "dummy1")
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),
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west: (
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(id: "dummy2"),
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(id: "A1", name: "A1"),
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(id: "dummy3"),
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(id: "A2", name: "A2"),
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(id: "A3", name: "A3"),
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(id: "dummy4"),
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(id: "WD3", name: "WD3"),
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),
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east: (
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(id: "RD1", name: "RD1"),
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(id: "RD2", name: "RD2"),
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)
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),
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ports-margins: (
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north: (-20%, -20%),
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east: (0%, 10%)
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),
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fill: util.colors.green,
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name: "Register\nFile"
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)
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element.alu(
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x: (rel: -.7, to: "IMem.center"),
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y: -7,
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w: 1.4, h: 2.8, id: "PCAdd",
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name: text("+", size: 1.5em),
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name-anchor: "name",
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fill: util.colors.pink
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)
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element.extender(
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x: (rel: 0, to: "RegFile.west"),
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y: (from: "PCAdd-port-out", to: "in"),
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w: 4, h: 1.5, id: "Ext",
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h-ratio: 50%,
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name: "Extend",
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name-anchor: "south",
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align-out: false,
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fill: util.colors.green
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)
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element.multiplexer(
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x: (rel: 3, to: "RegFile.east"),
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y: (from: "RegFile-port-RD2", to: "in0"),
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w: .5, h: 1.5, id: "SrcBMux",
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fill: util.colors.blue,
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h-ratio: 80%
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)
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element.alu(
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x: (rel: 2, to: "SrcBMux.east"),
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y: (from: "SrcBMux-port-out", to: "in2"),
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w: 1.4, h: 2.8, id: "ALU",
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name: rotate("ALU", -90deg),
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name-anchor: "name",
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fill: util.colors.pink
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)
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element.alu(
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x: (rel: 2, to: "SrcBMux.east"),
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y: (from: "Ext-port-out", to: "in2"),
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w: 1.4, h: 2.8, id: "JumpAdd",
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name: text("+", size: 1.5em),
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name-anchor: "name",
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fill: util.colors.pink
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)
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element.block(
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x: (rel: 4, to: "ALU.east"),
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y: (from: "ALU-port-out", to: "A"),
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w: 3, h: 4, id: "DMem",
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name: "Data\nMemory",
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ports: (
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north: (
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(id: "clk", clock: true, small: true),
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(id: "dummy1"),
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(id: "WE", name: "WE")
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),
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west: (
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(id: "A", name: "A"),
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(id: "WD", name: "WD")
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),
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east: (
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(id: "RD", name: "RD"),
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(id: "dummy2")
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)
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),
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ports-margins: (
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north: (-10%, -10%),
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west: (-20%, -30%),
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east: (-10%, -20%)
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),
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fill: util.colors.green
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)
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element.multiplexer(
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x: (rel: 3, to: "DMem.east"),
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y: (from: "DMem-port-RD", to: "in1"),
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w: .5, h: 1.5, id: "ResMux",
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entries: 2,
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fill: util.colors.blue,
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h-ratio: 80%
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)
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element.block(
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x: (rel: 0, to: "RegFile.west"),
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y: 3.5, w: 2.5, h: 5, id: "Ctrl",
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name: "Control\nUnit",
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name-anchor: "north",
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ports: (
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west: (
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(id: "op", name: "op"),
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(id: "funct3", name: "funct3"),
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(id: "funct7", name: [funct7#sub("[5]")]),
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(id: "zero", name: "Zero"),
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),
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east: (
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(id: "PCSrc"),
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(id: "ResSrc"),
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(id: "MemWrite"),
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(id: "ALUCtrl"),
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(id: "ALUSrc"),
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(id: "ImmSrc"),
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(id: "RegWrite"),
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)
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),
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ports-margins: (
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west: (40%, 0%)
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),
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fill: util.colors.orange
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)
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// Wires
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wire.wire(
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"wPCNext", ("PCMux-port-out", "PCBuf-port-in"),
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name: "PCNext"
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)
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wire.stub("PCBuf-port-clk", "north", name: "clk", length: 0.25)
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wire.wire(
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"wPC1", ("PCBuf-port-out", "IMem-port-A"),
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name: "PC"
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)
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wire.wire(
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"wPC2", ("PCBuf-port-out", "JumpAdd-port-in1"),
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style: "zigzag",
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zigzag-ratio: 1
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)
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wire.wire(
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"wPC3", ("PCBuf-port-out", "PCAdd-port-in1"),
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style: "zigzag",
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zigzag-ratio: 1
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)
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wire.intersection("wPC2.zig", radius: 2pt)
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wire.intersection("wPC2.zag", radius: 2pt)
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wire.stub("PCAdd-port-in2", "west", name: "4", length: 1.5)
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wire.wire(
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"wPC+4", ("PCAdd-port-out", "PCMux-port-in0"),
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style: "dodge",
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dodge-sides: ("east", "west"),
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dodge-y: -7.5,
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dodge-margins: (1.2, .5),
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name: "PC+4",
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name-pos: "start"
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)
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let mid = ("IMem-port-RD", 50%, "RegFile-port-A1")
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wire.wire(
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"wInstr", ("IMem-port-RD", mid),
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bus: true,
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name: "Instr",
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name-pos: "start"
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)
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draw.hide({
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draw.line(name: "bus-top",
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mid,
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(horizontal: (), vertical: "Ctrl-port-op")
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)
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draw.line(name: "bus-bot",
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mid,
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(horizontal: (), vertical: "Ext-port-in")
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)
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})
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wire.wire(
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"wInstrBus", ("bus-top.end", "bus-bot.end"),
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bus: true
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)
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wire.wire(
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"wOp", ("Ctrl-port-op", (horizontal: mid, vertical: ())),
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bus: true,
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reverse: true,
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slice: (6, 0)
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)
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wire.wire(
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"wF3", ("Ctrl-port-funct3", (horizontal: mid, vertical: ())),
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bus: true,
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reverse: true,
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slice: (14, 12)
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)
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wire.wire(
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"wF7", ("Ctrl-port-funct7", (horizontal: mid, vertical: ())),
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bus: true,
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reverse: true,
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slice: (30,)
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)
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wire.wire(
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"wA1", ("RegFile-port-A1", (horizontal: mid, vertical: ())),
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bus: true,
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reverse: true,
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slice: (19, 15)
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)
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wire.wire(
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"wA2", ("RegFile-port-A2", (horizontal: mid, vertical: ())),
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bus: true,
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reverse: true,
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slice: (24, 20)
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)
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wire.wire(
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"wA3", ("RegFile-port-A3", (horizontal: mid, vertical: ())),
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bus: true,
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reverse: true,
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slice: (11, 7)
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)
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wire.wire(
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"wExt", ("Ext-port-in", (horizontal: mid, vertical: ())),
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bus: true,
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reverse: true,
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slice: (31, 7)
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)
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wire.intersection("wF3.end", radius: 2pt)
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wire.intersection("wF7.end", radius: 2pt)
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wire.intersection("wA1.end", radius: 2pt)
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wire.intersection("wA2.end", radius: 2pt)
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wire.intersection("wA3.end", radius: 2pt)
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wire.stub("RegFile-port-clk", "north", name: "clk", length: 0.25)
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wire.wire("wRD2", ("RegFile-port-RD2", "SrcBMux-port-in0"))
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wire.wire(
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"wWD", ("RegFile-port-RD2", "DMem-port-WD"),
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style: "zigzag",
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zigzag-ratio: 1.5,
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name: "WriteData",
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name-pos: "end"
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)
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wire.intersection("wWD.zig", radius: 2pt)
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wire.wire(
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"wImmALU", ("Ext-port-out", "SrcBMux-port-in1"),
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style: "zigzag",
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zigzag-ratio: 2.5,
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name: "ImmExt",
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name-pos: "start"
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)
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wire.wire(
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"wImmJump", ("Ext-port-out", "JumpAdd-port-in2")
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)
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wire.intersection("wImmALU.zig", radius: 2pt)
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wire.wire(
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"wJumpPC", ("JumpAdd-port-out", "PCMux-port-in1"),
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style: "dodge",
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dodge-sides: ("east", "west"),
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dodge-y: -8,
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dodge-margins: (1, 1),
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name: "PCTarget",
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name-pos: "start"
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)
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wire.wire(
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"wSrcA", ("RegFile-port-RD1", "ALU-port-in1"),
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name: "SrcA",
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name-pos: "end"
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)
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wire.wire(
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"wSrcB", ("SrcBMux-port-out", "ALU-port-in2"),
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name: "SrcB",
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name-pos: "end"
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)
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wire.wire(
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"wZero", (
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("ALU.north-east", 50%, "ALU-port-out"),
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"Ctrl-port-zero"
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),
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style: "dodge",
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dodge-sides: ("east", "west"),
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dodge-y: 3,
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dodge-margins: (1.5, 1),
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name: "Zero",
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name-pos: "start"
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)
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wire.wire(
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"wALURes1", ("ALU-port-out", "DMem-port-A"),
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name: "ALUResult",
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name-pos: "start"
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)
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wire.wire(
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"wALURes2", ("ALU-port-out", "ResMux-port-in0"),
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style: "dodge",
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dodge-sides: ("east", "west"),
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dodge-y: 2,
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dodge-margins: (3, 2)
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)
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wire.intersection("wALURes2.start2", radius: 2pt)
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wire.stub("DMem-port-clk", "north", name: "clk", length: 0.25)
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wire.wire(
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"wRD", ("DMem-port-RD", "ResMux-port-in1"),
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name: "ReadData",
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name-pos: "start"
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)
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wire.wire(
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"wRes", ("ResMux-port-out", "RegFile-port-WD3"),
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style: "dodge",
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dodge-sides: ("east", "west"),
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dodge-y: -7.5,
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dodge-margins: (1, 2)
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)
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draw.content(
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"wRes.dodge-start",
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"Result",
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anchor: "south-east",
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padding: 5pt
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)
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// Other wires
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draw.group({
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draw.stroke(util.colors.blue)
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draw.line(name: "wPCSrc",
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"Ctrl-port-PCSrc",
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(horizontal: "RegFile.east", vertical: ()),
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(horizontal: (), vertical: (rel: (0, 0.5), to: "Ctrl.north")),
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(horizontal: "PCMux.north", vertical: ()),
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"PCMux.north"
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)
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draw.line(name: "wResSrc",
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"Ctrl-port-ResSrc",
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(horizontal: "ResMux.north", vertical: ()),
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"ResMux.north"
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)
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draw.line(name: "wMemWrite",
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"Ctrl-port-MemWrite",
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(horizontal: "DMem-port-WE", vertical: ()),
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"DMem-port-WE"
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)
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draw.line(name: "wALUCtrl",
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"Ctrl-port-ALUCtrl",
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(horizontal: "ALU.north", vertical: ()),
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"ALU.north"
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)
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draw.line(name: "wALUSrc",
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"Ctrl-port-ALUSrc",
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(horizontal: "SrcBMux.north", vertical: ()),
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"SrcBMux.north"
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)
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draw.line(name: "wImmSrc",
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"Ctrl-port-ImmSrc",
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(rel: (1, 0), to: (horizontal: "RegFile.east", vertical: ())),
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(horizontal: (), vertical: (rel: (0, -.5), to: "RegFile.south")),
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(horizontal: "Ext.north", vertical: ()),
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"Ext.north"
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)
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draw.line(name: "wRegWrite",
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"Ctrl-port-RegWrite",
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(rel: (.5, 0), to: (horizontal: "RegFile.east", vertical: ())),
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(horizontal: (), vertical: ("Ctrl.south", 50%, "RegFile.north")),
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(horizontal: "RegFile-port-WE3", vertical: ()),
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"RegFile-port-WE3"
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)
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let names = (
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"PCSrc": "PCSrc",
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"ResSrc": "ResultSrc",
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"MemWrite": "MemWrite",
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"ALUCtrl": [ALUControl#sub("[2:0]")],
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"ALUSrc": "ALUSrc",
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"ImmSrc": [ImmSrc#sub("[1:0]")],
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"RegWrite": "RegWrite"
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)
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for (port, name) in names {
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draw.content("Ctrl-port-"+port, name, anchor: "south-west", padding: 3pt)
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}
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})
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}) |