diff --git a/README.md b/README.md index 60132f4..2b6cb22 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ Circuiteria is a [Typst](https://typst.app) package for drawing block circuit diagrams using the [CeTZ](https://typst.app/universe/package/cetz) package.

- Perry the platypus + A platypus / Perry the Platypus meme made with colored rounded rectangles

## Examples @@ -11,17 +11,17 @@ Circuiteria is a [Typst](https://typst.app) package for drawing block circuit di - + Block diagram of a multi-cycle RISC-V FPGA processor - A bit of eveything + A bit of everything - + Block diagram of a single-cycle RISC-V processor @@ -31,12 +31,12 @@ Circuiteria is a [Typst](https://typst.app) package for drawing block circuit di - + Top-level block diagram of a single-cycle RISC-V processor - + Block diagram of a simple single-cycle RISC-V ALU @@ -56,7 +56,7 @@ For more information, see the [manual](manual.pdf) To use this package, simply import [circuiteria](https://typst.app/universe/package/circuiteria) and call the `circuit` function: ```typ -#import "@preview/circuiteria:0.2.0" +#import "@preview/circuiteria:0.2.1" #circuiteria.circuit({ import circuiteria: * ... diff --git a/doc/example.typ b/doc/example.typ index 7e7af59..32f35b8 100644 --- a/doc/example.typ +++ b/doc/example.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "../src/circuit.typ": circuit #import "../src/util.typ" diff --git a/doc/examples.typ b/doc/examples.typ index d968bf9..a182e59 100644 --- a/doc/examples.typ +++ b/doc/examples.typ @@ -56,7 +56,7 @@ for i in range(3) { ```) #let wires = example(``` -for i in range(3) { +for i in range(4) { draw.circle((i * 3, 0), radius: .1, name: "p" + str(i * 2)) draw.circle((i * 3 + 2, 1), radius: .1, name: "p" + str(i * 2 + 1)) draw.content((i * 3 + 1, -1), raw(wire.wire-styles.at(i))) @@ -65,6 +65,10 @@ wire.wire("w1", ("p0", "p1"), style: "direct") wire.wire("w2", ("p2", "p3"), style: "zigzag") wire.wire("w3", ("p4", "p5"), style: "dodge", dodge-y: -0.5, dodge-margins: (0.5, 0.5)) +wire.wire("w4", ("p6","p7"), style: "guided", + guided-center:(20%, 40%), guided-margins: (90%,87%), + guided-sides: ("north","south")) + ```, vertical: true) #let stub = example(``` @@ -115,6 +119,46 @@ gates.gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5) gates.gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") ```, vertical: true) +#let iec-gate-and = example(``` +gates.iec-gate-and(x: 0, y: 0, w: 1.5, h: 1.5) +gates.iec-gate-and(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") +```, vertical: true) + +#let iec-gate-nand = example(``` +gates.iec-gate-nand(x: 0, y: 0, w: 1.5, h: 1.5) +gates.iec-gate-nand(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") +```, vertical: true) + +#let iec-gate-or = example(``` +gates.iec-gate-or(x: 0, y: 0, w: 1.5, h: 1.5) +gates.iec-gate-or(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") +```, vertical: true) + +#let iec-gate-nor = example(``` +gates.iec-gate-nor(x: 0, y: 0, w: 1.5, h: 1.5) +gates.iec-gate-nor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") +```, vertical: true) + +#let iec-gate-xor = example(``` +gates.iec-gate-xor(x: 0, y: 0, w: 1.5, h: 1.5) +gates.iec-gate-xor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") +```, vertical: true) + +#let iec-gate-xnor = example(``` +gates.iec-gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5) +gates.iec-gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") +```, vertical: true) + +#let iec-gate-buf = example(``` +gates.iec-gate-buf(x: 0, y: 0, w: 1.5, h: 1.5) +gates.iec-gate-buf(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") +```, vertical: true) + +#let iec-gate-not = example(``` +gates.iec-gate-not(x: 0, y: 0, w: 1.5, h: 1.5) +gates.iec-gate-not(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all") +```, vertical: true) + #let group = example(``` element.group( id: "g1", name: "Group 1", stroke: (dash: "dashed"), @@ -147,4 +191,4 @@ wire.wire("w1", ((0, 0), (1, 1)), style: "zigzag") wire.wire("w2", ((0, 0), (1, -.5)), style: "zigzag", zigzag-ratio: 80%) wire.intersection("w1.zig") -```) \ No newline at end of file +```) diff --git a/gallery/platypus.pdf b/gallery/platypus.pdf deleted file mode 100644 index e288eb0..0000000 Binary files a/gallery/platypus.pdf and /dev/null differ diff --git a/gallery/platypus.png b/gallery/platypus.png index a52e375..7e0a912 100644 Binary files a/gallery/platypus.png and b/gallery/platypus.png differ diff --git a/gallery/platypus.typ b/gallery/platypus.typ index 4cc190d..f67021d 100644 --- a/gallery/platypus.typ +++ b/gallery/platypus.typ @@ -1,4 +1,4 @@ -#import "../src/lib.typ": * +#import "@preview/circuiteria:0.2.1": * #set page(width: auto, height: auto, margin: .5cm) diff --git a/gallery/test.pdf b/gallery/test.pdf deleted file mode 100644 index 83047e2..0000000 Binary files a/gallery/test.pdf and /dev/null differ diff --git a/gallery/test.png b/gallery/test.png index b6e812c..c4e9480 100644 Binary files a/gallery/test.png and b/gallery/test.png differ diff --git a/gallery/test.typ b/gallery/test.typ index fe07b62..dab21cc 100644 --- a/gallery/test.typ +++ b/gallery/test.typ @@ -1,4 +1,4 @@ -#import "../src/lib.typ": circuit, element, util, wire +#import "@preview/circuiteria:0.2.1": circuit, element, util, wire #set page(width: auto, height: auto, margin: .5cm) diff --git a/gallery/test2.pdf b/gallery/test2.pdf deleted file mode 100644 index dc672ed..0000000 Binary files a/gallery/test2.pdf and /dev/null differ diff --git a/gallery/test2.png b/gallery/test2.png index b6e812c..c4e9480 100644 Binary files a/gallery/test2.png and b/gallery/test2.png differ diff --git a/gallery/test2.typ b/gallery/test2.typ index f8ea126..dc877e9 100644 --- a/gallery/test2.typ +++ b/gallery/test2.typ @@ -1,4 +1,4 @@ -#import "../src/lib.typ": circuit, element, util, wire +#import "@preview/circuiteria:0.2.1": circuit, element, util, wire #set page(width: auto, height: auto, margin: .5cm) diff --git a/gallery/test3.pdf b/gallery/test3.pdf deleted file mode 100644 index d027d37..0000000 Binary files a/gallery/test3.pdf and /dev/null differ diff --git a/gallery/test3.png b/gallery/test3.png index 2ed46d0..8af0ba5 100644 Binary files a/gallery/test3.png and b/gallery/test3.png differ diff --git a/gallery/test3.typ b/gallery/test3.typ index 89db692..9d93b75 100644 --- a/gallery/test3.typ +++ b/gallery/test3.typ @@ -1,5 +1,4 @@ -#import "@preview/cetz:0.3.2": draw -#import "../src/lib.typ": circuit, element, util, wire +#import "@preview/circuiteria:0.2.1": circuit, element, util, wire #set page(width: auto, height: auto, margin: .5cm) diff --git a/gallery/test4.pdf b/gallery/test4.pdf deleted file mode 100644 index 0224fb0..0000000 Binary files a/gallery/test4.pdf and /dev/null differ diff --git a/gallery/test4.png b/gallery/test4.png index e7666f6..4f36ffc 100644 Binary files a/gallery/test4.png and b/gallery/test4.png differ diff --git a/gallery/test4.typ b/gallery/test4.typ index 08f8d00..30a5067 100644 --- a/gallery/test4.typ +++ b/gallery/test4.typ @@ -1,5 +1,5 @@ -#import "@preview/cetz:0.3.2": draw -#import "../src/lib.typ": * +#import "/src/cetz.typ": draw +#import "@preview/circuiteria:0.2.1": * #set page(width: auto, height: auto, margin: .5cm) diff --git a/gallery/test5.pdf b/gallery/test5.pdf deleted file mode 100644 index f616a95..0000000 Binary files a/gallery/test5.pdf and /dev/null differ diff --git a/gallery/test5.png b/gallery/test5.png index b70bb2c..e23a31f 100644 Binary files a/gallery/test5.png and b/gallery/test5.png differ diff --git a/gallery/test5.typ b/gallery/test5.typ index ebf6e77..8696794 100644 --- a/gallery/test5.typ +++ b/gallery/test5.typ @@ -1,5 +1,5 @@ -#import "@preview/cetz:0.3.2": draw -#import "../src/lib.typ": * +#import "/src/cetz.typ": draw +#import "@preview/circuiteria:0.2.1": * #set page(width: auto, height: auto, margin: .5cm) diff --git a/gallery/test6.pdf b/gallery/test6.pdf deleted file mode 100644 index 0fbaa69..0000000 Binary files a/gallery/test6.pdf and /dev/null differ diff --git a/gallery/test6.png b/gallery/test6.png index be04367..409663e 100644 Binary files a/gallery/test6.png and b/gallery/test6.png differ diff --git a/gallery/test6.typ b/gallery/test6.typ index ba76c94..2c53f18 100644 --- a/gallery/test6.typ +++ b/gallery/test6.typ @@ -1,5 +1,5 @@ -#import "@preview/cetz:0.3.2": draw, vector -#import "../src/lib.typ": * +#import "/src/cetz.typ": draw +#import "@preview/circuiteria:0.2.1": * #set page(width: auto, height: auto, margin: .5cm) diff --git a/gallery/test7.png b/gallery/test7.png new file mode 100644 index 0000000..cfe3ee4 Binary files /dev/null and b/gallery/test7.png differ diff --git a/gallery/test7.typ b/gallery/test7.typ new file mode 100644 index 0000000..196339f --- /dev/null +++ b/gallery/test7.typ @@ -0,0 +1,97 @@ +#import "@preview/circuiteria:0.2.1": circuit, element, util, wire + +#set page(width: auto, height: auto, margin: .5cm) + +#circuit({ + element.iec-gate-buf( + x: 0, + y: 0, + w: 2, + h: 2, + id: "iec-buf", + inputs: 1, + ) + wire.stub("iec-buf-port-in0", "west") + + element.iec-gate-not( + x: 3, + y: 0, + w: 2, + h: 2, + id: "iec-not", + inputs: 1, + ) + wire.stub("iec-not-port-in0", "west") + + element.iec-gate-and( + id: "iec-and", + x: 0, + y: -3, + w: 2, + h: 2, + inputs: 2, + ) + for i in range(2) { + wire.stub("iec-and-port-in" + str(i), "west") + } + + element.iec-gate-nand( + id: "iec-nand", + x: 3, + y: -3, + w: 2, + h: 2, + inputs: 2, + ) + for i in range(2) { + wire.stub("iec-nand-port-in" + str(i), "west") + } + + element.iec-gate-or( + id: "iec-or", + x: 0, + y: -6, + w: 2, + h: 2, + inputs: 2, + ) + for i in range(2) { + wire.stub("iec-or-port-in" + str(i), "west") + } + + element.iec-gate-nor( + id: "iec-nor", + x: 3, + y: -6, + w: 2, + h: 2, + inputs: 2, + ) + for i in range(2) { + wire.stub("iec-nor-port-in" + str(i), "west") + } + + element.iec-gate-xor( + id: "iec-xor", + x: 0, + y: -9, + w: 2, + h: 2, + inputs: 2, + ) + for i in range(2) { + wire.stub("iec-xor-port-in" + str(i), "west") + } + + element.iec-gate-xnor( + id: "iec-nxor", + x: 3, + y: -9, + w: 2, + h: 2, + inputs: 2, + ) + for i in range(2) { + wire.stub("iec-nxor-port-in" + str(i), "west") + } +}) \ No newline at end of file diff --git a/manual.pdf b/manual.pdf index 8d1abf7..f4e1052 100644 Binary files a/manual.pdf and b/manual.pdf differ diff --git a/manual.typ b/manual.typ index 7a327d6..ebe0c88 100644 --- a/manual.typ +++ b/manual.typ @@ -1,5 +1,5 @@ #import "@preview/tidy:0.4.1" -#import "@preview/cetz:0.3.2": draw, canvas +#import "/src/cetz.typ": draw, canvas #import "src/lib.typ" #import "doc/examples.typ" #import "src/circuit.typ": circuit @@ -105,7 +105,7 @@ This package provides a way to make beautiful block circuit diagrams using the C Simply import Circuiteria and call the `circuit` function: #pad(left: 1em)[```typ -#import "@preview/circuiteria:0.2.0" +#import "@preview/circuiteria:0.2.1" #circuiteria.circuit({ import circuiteria: * ... @@ -195,7 +195,12 @@ If you have installed Circuiteria directly in your project, import #link("src/li read("src/elements/logic/and.typ") + "\n" + read("src/elements/logic/buf.typ") + "\n" + read("src/elements/logic/or.typ") + "\n" + - read("src/elements/logic/xor.typ"), + read("src/elements/logic/xor.typ") + "\n" + + read("src/elements/logic/iec_gate.typ") + "\n" + + read("src/elements/logic/iec_and.typ") + "\n" + + read("src/elements/logic/iec_buf.typ") + "\n" + + read("src/elements/logic/iec_or.typ") + "\n" + + read("src/elements/logic/iec_xor.typ"), name: "gates", old-syntax: true, scope: ( diff --git a/src/cetz.typ b/src/cetz.typ new file mode 100644 index 0000000..980a619 --- /dev/null +++ b/src/cetz.typ @@ -0,0 +1 @@ +#import "@preview/cetz:0.3.4": * \ No newline at end of file diff --git a/src/circuit.typ b/src/circuit.typ index 7a701c7..f89389f 100644 --- a/src/circuit.typ +++ b/src/circuit.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": canvas +#import "/src/cetz.typ": canvas #import "@preview/tidy:0.3.0" /// Draws a block circuit diagram @@ -9,6 +9,5 @@ /// - length (length, ratio): Optional base unit /// -> none #let circuit(body, length: 2em) = { - set text(font: "Source Sans 3") canvas(length: length, body) -} \ No newline at end of file +} diff --git a/src/element.typ b/src/element.typ index 3bf0e17..89c3032 100644 --- a/src/element.typ +++ b/src/element.typ @@ -11,5 +11,10 @@ #import "elements/logic/or.typ": gate-or, gate-nor #import "elements/logic/xor.typ": gate-xor, gate-xnor #import "elements/logic/buf.typ": gate-buf, gate-not +#import "elements/logic/iec_gate.typ": iec-gate +#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand +#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not +#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor +#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor #import "elements/group.typ": group \ No newline at end of file diff --git a/src/elements/alu.typ b/src/elements/alu.typ index 9a8cb82..98564e3 100644 --- a/src/elements/alu.typ +++ b/src/elements/alu.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "element.typ" #import "ports.typ": add-port diff --git a/src/elements/block.typ b/src/elements/block.typ index 84623fe..5ff6928 100644 --- a/src/elements/block.typ +++ b/src/elements/block.typ @@ -1,9 +1,9 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "element.typ" -#let draw-shape(id, tl, tr, br, bl, fill, stroke) = { +#let draw-shape(id, tl, tr, br, bl, fill, stroke, radius: 0.5em) = { let f = draw.rect( - radius: 0.5em, + radius: radius, inset: 0.5em, fill: fill, stroke: stroke, @@ -16,7 +16,8 @@ /// Draws a block element /// /// #examples.block -/// For parameters description, see #doc-ref("element.elmt") +/// For other parameters description, see #doc-ref("element.elmt") +/// - radius (number, length, ratio, dictionary): The corner radius of the block. See CeTZ documentation for more information #let block( x: none, y: none, @@ -27,13 +28,14 @@ ports: (), ports-margins: (), fill: none, + radius: 0.5em, stroke: black + 1pt, id: "", debug: ( ports: false ) ) = element.elmt( - draw-shape: draw-shape, + draw-shape: draw-shape.with(radius: radius), x: x, y: y, w: w, @@ -46,4 +48,4 @@ stroke: stroke, id: id, debug: debug -) \ No newline at end of file +) diff --git a/src/elements/element.typ b/src/elements/element.typ index 635fc0b..09adfd3 100644 --- a/src/elements/element.typ +++ b/src/elements/element.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw, coordinate +#import "/src/cetz.typ": draw, coordinate #import "ports.typ": add-ports, add-port #import "../util.typ" diff --git a/src/elements/extender.typ b/src/elements/extender.typ index a1b99e0..cb40ae0 100644 --- a/src/elements/extender.typ +++ b/src/elements/extender.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "element.typ" #import "ports.typ": add-port diff --git a/src/elements/group.typ b/src/elements/group.typ index 1f3e41c..994072c 100644 --- a/src/elements/group.typ +++ b/src/elements/group.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw, coordinate +#import "/src/cetz.typ": draw, coordinate #import "../util.typ" /// Draws a group of elements diff --git a/src/elements/logic/and.typ b/src/elements/logic/and.typ index f32eb21..4b86405 100644 --- a/src/elements/logic/and.typ +++ b/src/elements/logic/and.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "gate.typ" #let draw-shape(id, tl, tr, br, bl, fill, stroke) = { diff --git a/src/elements/logic/buf.typ b/src/elements/logic/buf.typ index 3db75a9..12389a6 100644 --- a/src/elements/logic/buf.typ +++ b/src/elements/logic/buf.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "gate.typ" #let draw-shape(id, tl, tr, br, bl, fill, stroke) = { diff --git a/src/elements/logic/gate.typ b/src/elements/logic/gate.typ index 7350a70..bd0fb23 100644 --- a/src/elements/logic/gate.typ +++ b/src/elements/logic/gate.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw, coordinate +#import "/src/cetz.typ": draw, coordinate #import "../ports.typ": add-ports, add-port #import "../element.typ" @@ -63,6 +63,12 @@ if to == "out" { dy = height / 2 } else { + let all-ports = range(inputs).map(i => "in" + str(i)) + let i = all-ports.position(p => p == to) + assert( + i != none, + message: "Unknown port '" + y.to + "' must be one of " + repr(all-ports) + ) dy = height * (i + 0.5) / inputs } diff --git a/src/elements/logic/iec_and.typ b/src/elements/logic/iec_and.typ new file mode 100644 index 0000000..ed51fc3 --- /dev/null +++ b/src/elements/logic/iec_and.typ @@ -0,0 +1,70 @@ +#import "/src/cetz.typ": draw +// #import "iec_gate.typ" as iec-gate +#import "iec_gate.typ" as iec-gate + + +/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()` +/// +/// For parameters, see #doc-ref("gates.iec-gate") +/// #examples.iec-gate-and +#let iec-gate-and( + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + debug: ( + ports: false + ), +) = { + iec-gate.iec-gate( + x: x, + y: y, + w: w, + h: h, + inputs: inputs, + fill: fill, + stroke: stroke, + id: id, + inverted: inverted, + debug: debug, + symbol: $amp$, + ) + +} + +/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()` +/// +/// For parameters, see #doc-ref("gates.iec-gate") +/// #examples.iec-gate-nand +#let iec-gate-nand( + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + debug: ( + ports: false + ), +) = { + iec-gate-and( + x: x, + y: y, + w: w, + h: h, + inputs: inputs, + fill: fill, + stroke: stroke, + id: id, + inverted: if inverted != "all" {inverted + ("out",)} else {inverted}, + debug: debug, + ) +} \ No newline at end of file diff --git a/src/elements/logic/iec_buf.typ b/src/elements/logic/iec_buf.typ new file mode 100644 index 0000000..34c8a76 --- /dev/null +++ b/src/elements/logic/iec_buf.typ @@ -0,0 +1,68 @@ +#import "/src/cetz.typ": draw +#import "iec_gate.typ" as iec-gate + + +/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()` +/// +/// For parameters, see #doc-ref("gates.iec-gate") +/// #examples.iec-gate-buf +#let iec-gate-buf( + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + debug: ( + ports: false, + ), +) = { + iec-gate.iec-gate( + x: x, + y: y, + w: w, + h: h, + inputs: inputs, + fill: fill, + stroke: stroke, + id: id, + inverted: inverted, + debug: debug, + symbol: "1", + ) +} + +/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()` +/// +/// For parameters, see #doc-ref("gates.iec-gate") +/// #examples.iec-gate-not +#let iec-gate-not( + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + debug: ( + ports: false, + ), +) = { + iec-gate-buf( + x: x, + y: y, + w: w, + h: h, + inputs: inputs, + fill: fill, + stroke: stroke, + id: id, + inverted: if inverted != "all" { inverted + ("out",) } else { inverted }, + debug: debug, + ) +} diff --git a/src/elements/logic/iec_gate.typ b/src/elements/logic/iec_gate.typ new file mode 100644 index 0000000..08d97f1 --- /dev/null +++ b/src/elements/logic/iec_gate.typ @@ -0,0 +1,125 @@ +#import "/src/cetz.typ": draw, coordinate +#import "../ports.typ": add-ports, add-port +#import "../element.typ" + +#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = { + let shapes = draw.rect( + inset: 0.5em, + fill: fill, + stroke: stroke, + name: id, + bl, tr + ) + shapes += draw.content( + id + ".center", + [*$ symbol $*] + ) + return (shapes, tl, tr, br, bl) +} + +/// Draws a logic gate. This function is also available as `element.iec-gate()` +/// +/// - draw-shape (function): see #doc-ref("element.elmt") +/// - x (number, dictionary): see #doc-ref("element.elmt") +/// - y (number, dictionary): see #doc-ref("element.elmt") +/// - w (number): see #doc-ref("element.elmt") +/// - h (number): see #doc-ref("element.elmt") +/// - inputs (int): The number of inputs +/// - fill (none, color): see #doc-ref("element.elmt") +/// - stroke (stroke): see #doc-ref("element.elmt") +/// - id (str): see #doc-ref("element.elmt") +/// - inverted (str, array): Either "all" or an array of port ids to display as inverted +/// - inverted-radius (number): The radius of inverted ports dot +/// - debug (dictionary): see #doc-ref("element.elmt") +/// - symbol (str): The symbol to display at the center of the gate +#let iec-gate( + draw-shape: default-draw-shape, + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + inverted-radius: 0.1, + debug: ( + ports: false + ), + symbol: "", +) = draw.get-ctx(ctx => { + let width = w + let height = h + + let x = x + let y = y + if x == none { panic("Parameter x must be set") } + if y == none { panic("Parameter y must be set") } + if w == none { panic("Parameter w must be set") } + if h == none { panic("Parameter h must be set") } + + if (type(x) == dictionary) { + let offset = x.rel + let to = x.to + let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to)) + x = to-pos.at(0) + } + + if (type(y) == dictionary) { + let from = y.from + let to = y.to + + let dy + if to == "out" { + dy = height / 2 + } else { + dy = height * (i + 0.5) / inputs + } + + let (ctx, from-pos) = coordinate.resolve(ctx, from) + y = from-pos.at(1) + dy - height + } + + let tl = (x, y + height) + let tr = (x + width, y + height) + let br = (x + width, y) + let bl = (x, y) + + // Workaround because CeTZ needs to have all draw functions in the body + let func = {} + (func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) + func + + let space = 100% / inputs + for i in range(inputs) { + let pct = (i + 0.5) * space + let port-pos = (tl, pct, bl) + let port-name = "in" + str(i) + if inverted == "all" or port-name in inverted { + draw.circle( + port-pos, + radius: inverted-radius, + anchor: "east", + stroke: stroke + ) + port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos) + } + add-port( + id, "west", + (id: port-name), port-pos, + debug: debug.ports + ) + } + + let out-pos = id + ".east" + if inverted == "all" or "out" in inverted { + draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke) + out-pos = (rel: (2 * inverted-radius, 0), to: out-pos) + } + add-port( + id, "east", + (id: "out"), out-pos, + debug: debug.ports + ) +}) \ No newline at end of file diff --git a/src/elements/logic/iec_or.typ b/src/elements/logic/iec_or.typ new file mode 100644 index 0000000..0c7836e --- /dev/null +++ b/src/elements/logic/iec_or.typ @@ -0,0 +1,67 @@ +#import "/src/cetz.typ": draw +#import "iec_gate.typ" as iec-gate + +/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()` +/// +/// For parameters, see #doc-ref("gates.iec-gate") +/// #examples.iec-gate-or +#let iec-gate-or( + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + debug: ( + ports: false + ) +) = { + iec-gate.iec-gate( + x: x, + y: y, + w: w, + h: h, + inputs: inputs, + fill: fill, + stroke: stroke, + id: id, + inverted: inverted, + debug: debug, + symbol: $>= 1$, + ) +} + +/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()` +/// +/// For parameters, see #doc-ref("gates.iec-gate") +/// #examples.iec-gate-nor +#let iec-gate-nor( + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + debug: ( + ports: false + ) +) = { + iec-gate-or( + x: x, + y: y, + w: w, + h: h, + inputs: inputs, + fill: fill, + stroke: stroke, + id: id, + inverted: if inverted != "all" {inverted + ("out",)} else {inverted}, + debug: debug + ) +} \ No newline at end of file diff --git a/src/elements/logic/iec_xor.typ b/src/elements/logic/iec_xor.typ new file mode 100644 index 0000000..659c055 --- /dev/null +++ b/src/elements/logic/iec_xor.typ @@ -0,0 +1,67 @@ +#import "/src/cetz.typ": draw +#import "iec_gate.typ" as iec-gate + +/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()` +/// +/// For parameters, see #doc-ref("gates.iec-gate") +/// #examples.iec-gate-xor +#let iec-gate-xor( + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + debug: ( + ports: false + ) +) = { + iec-gate.iec-gate( + x: x, + y: y, + w: w, + h: h, + inputs: inputs, + fill: fill, + stroke: stroke, + id: id, + inverted: inverted, + debug: debug, + symbol: $= 1$, + ) +} + +/// Draws an IEC-XNOR gate. This function is also available as `element.iec-gate-xnor()` +/// +/// For parameters, see #doc-ref("gates.iec-gate") +/// #examples.iec-gate-xnor +#let iec-gate-xnor( + x: none, + y: none, + w: none, + h: none, + inputs: 2, + fill: none, + stroke: black + 1pt, + id: "", + inverted: (), + debug: ( + ports: false + ) +) = { + iec-gate-xor( + x: x, + y: y, + w: w, + h: h, + inputs: inputs, + fill: fill, + stroke: stroke, + id: id, + inverted: if inverted != "all" {inverted + ("out",)} else {inverted}, + debug: debug + ) +} \ No newline at end of file diff --git a/src/elements/logic/or.typ b/src/elements/logic/or.typ index dca0f9b..b3af00e 100644 --- a/src/elements/logic/or.typ +++ b/src/elements/logic/or.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "gate.typ" #let draw-shape(id, tl, tr, br, bl, fill, stroke) = { diff --git a/src/elements/logic/xor.typ b/src/elements/logic/xor.typ index 3f226a8..0ed08f0 100644 --- a/src/elements/logic/xor.typ +++ b/src/elements/logic/xor.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "gate.typ" #let space = 10% diff --git a/src/elements/multiplexer.typ b/src/elements/multiplexer.typ index d7c29eb..bb36b7c 100644 --- a/src/elements/multiplexer.typ +++ b/src/elements/multiplexer.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "../util.typ" #import "element.typ" #import "ports.typ": add-port diff --git a/src/elements/ports.typ b/src/elements/ports.typ index 951fa4a..b24cdfc 100644 --- a/src/elements/ports.typ +++ b/src/elements/ports.typ @@ -1,4 +1,4 @@ -#import "@preview/cetz:0.3.2": draw +#import "/src/cetz.typ": draw #import "../util.typ": rotate-anchor #let add-port( diff --git a/src/gates.typ b/src/gates.typ index 85ba178..616cc57 100644 --- a/src/gates.typ +++ b/src/gates.typ @@ -2,4 +2,9 @@ #import "elements/logic/and.typ": gate-and, gate-nand #import "elements/logic/or.typ": gate-or, gate-nor #import "elements/logic/xor.typ": gate-xor, gate-xnor -#import "elements/logic/buf.typ": gate-buf, gate-not \ No newline at end of file +#import "elements/logic/buf.typ": gate-buf, gate-not +#import "elements/logic/iec_gate.typ": iec-gate +#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand +#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor +#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not +#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor diff --git a/src/lib.typ b/src/lib.typ index 7f27208..3970ead 100644 --- a/src/lib.typ +++ b/src/lib.typ @@ -1,4 +1,5 @@ -#let version = version(0, 2, 0) +#let version = version(0, 2, 1) +#let name = "circuiteria" #import "circuit.typ": circuit #import "element.typ" diff --git a/src/wire.typ b/src/wire.typ index 8300a2c..cbf7c4b 100644 --- a/src/wire.typ +++ b/src/wire.typ @@ -1,9 +1,9 @@ -#import "@preview/cetz:0.3.2": draw, coordinate +#import "/src/cetz.typ": draw, coordinate #import "util.typ": opposite-anchor /// List of valid wire styles /// #examples.wires -#let wire-styles = ("direct", "zigzag", "dodge") +#let wire-styles = ("direct", "zigzag", "dodge", "guided") #let signal-width = 1pt #let bus-width = 1.5pt @@ -109,6 +109,88 @@ return (points, anchors) } +#let get-guided-wire(pts, margins, sides, center-guides, ctx) = { + let start = pts.first() + let end = pts.last() + let (margin-start, margin-end) = margins + let (side-start, side-end) = sides + let (center_horizontal, center_vertical) = center-guides + + let (ctx, p0) = coordinate.resolve(ctx, start) + let (ctx, p6) = coordinate.resolve(ctx, end) + p0 = (x: p0.first(), y: p0.at(1)) + p6 = (x: p6.first(), y: p6.at(1)) + + let box_width = calc.abs(p6.x - p0.x) + let box_height = calc.abs(p6.y - p0.y) + + // finding correct dx and dy + let dx1 = box_width * margin-start / 100% + if side-start == "west" { + dx1 *= -1 + } else if side-start == "north" or side-start == "south" { dx1 = 0} + + let dx2 = box_width * margin-end / 100% + if side-end == "west" { + dx2 *= -1 + } else if side-end == "north" or side-end == "south" { dx2 = 0} + + let dy1 = box_height * margin-start / 100% + if side-start == "south" { + dy1 *= -1 + } else if side-start == "west" or side-start == "east" { dy1 = 0} + + let dy2 = box_height * margin-end / 100% + if side-end == "south" { + dy2 *= -1 + } else if side-end == "west" or side-end == "east" { dy2 = 0} + + + // points that are closest to the edge points + let p1 = (p0.x + dx1, p0.y + dy1) + let p5 = (p6.x + dx2, p6.y + dy2) + + + // middle point + let center_x = p0.x + box_width * center_horizontal / 100% + let center_y = p0.y + box_height * center_vertical / 100% + let p3 = (center_x, center_y) + + // setting up the points for that touch the guides + let p2 = (0,0) + let p4 = (0,0) + if side-start in ("north", "south") { + p2 = (horizontal: p3, vertical: p1) + } else { + p2 = (horizontal: p1, vertical: p3) + } + if side-end in ("north", "south") { + p4 = (horizontal: p3, vertical: p5) + } else if side-end in ("east", "west") { + p4 = (horizontal: p5, vertical: p3) + } + + // returning + let points = ( + start, + p1, + p2, + p3, + p4, + p5, + end + ) + let anchors = ( + "start": start, + "start2": points.at(1), + "guide-start": points.at(2), + "center": points.at(3), + "guide-end": points.at(4), + "end2": points.at(5), + "end": end + ) + return (points, anchors) +} /// Draws a wire between two points /// - id (str): The wire's id, for future reference (anchors) /// - pts (array): The two points (as CeTZ compatible coordinates, i.e. XY, relative positions, ids, etc.) @@ -127,6 +209,9 @@ /// - dodge-y (number): Y position to dodge the wire to (only with style "dodge") /// - dodge-sides (array): The start and end sides (going out of the connected element) of the wire (only with style "dodge") /// - dodge-margins (array): The start and end margins (i.e. space before dodging) of the wire (only with style "dodge") +/// - guided-center (array): the horizontal and vertical guides of the center guides (only with style "guided") +/// - guided-margins (array): the start and end of guided margins of the wire (only with style "guided") +/// - guided-sides (array): the side of start and end array (must be either "north", "south", "west", "east") (only work with style "guided") #let wire( id, pts, bus: false, @@ -137,6 +222,9 @@ dashed: false, style: "direct", reverse: false, + guided-center: (50%, 50%), + guided-margins: (5%, 5%), + guided-sides: ("east", "west"), directed: false, rotate-name: true, zigzag-ratio: 50%, @@ -178,6 +266,14 @@ dodge-sides, ctx ) + } else if style == "guided" { + (points, anchors) = get-guided-wire( + pts, + guided-margins, + guided-sides, + guided-center, + ctx + ) } let mark = (fill: color) @@ -303,4 +399,4 @@ name ) } -} \ No newline at end of file +} diff --git a/typst.toml b/typst.toml index 39cff5b..b83700a 100644 --- a/typst.toml +++ b/typst.toml @@ -1,7 +1,7 @@ [package] name = "circuiteria" -version = "0.2.0" -compiler = "0.13.0" +version = "0.2.1" +compiler = "0.13.1" repository = "https://git.kb28.ch/HEL/circuiteria" entrypoint = "src/lib.typ" authors = [ @@ -9,6 +9,6 @@ authors = [ ] categories = [ "visualization" ] license = "Apache-2.0" -description = "Drawing block circuits with Typst made easy, using CeTZ" +description = "Drawing block circuits made easy, using CeTZ" keywords = [ "circuit", "block", "draw" ] exclude = [ "gallery", "justfile", "doc" ] \ No newline at end of file