Merge pull request 'feature: added guided wire style' (#14) from Shmerlard/circuiteria:dev into dev

Reviewed-on: #14
Reviewed-by: Louis Heredero <louis@herdac.ch>

README.md

@@ -56,7 +56,7 @@ For more information, see the [manual](manual.pdf)
 
 To use this package, simply import [circuiteria](https://typst.app/universe/package/circuiteria) and call the `circuit` function:
 ```typ
-#import "@preview/circuiteria:0.1.0"
+#import "@preview/circuiteria:0.2.0"
 #circuiteria.circuit({
   import circuiteria: *
   ...

doc/example.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "../src/circuit.typ": circuit
 #import "../src/util.typ"
 

doc/examples.typ

@@ -56,7 +56,7 @@ for i in range(3) {
 ```)
 
 #let wires = example(```
-for i in range(3) {
+for i in range(4) {
   draw.circle((i * 3, 0), radius: .1, name: "p" + str(i * 2))
   draw.circle((i * 3 + 2, 1), radius: .1, name: "p" + str(i * 2 + 1))
   draw.content((i * 3 + 1, -1), raw(wire.wire-styles.at(i)))
@@ -65,6 +65,10 @@ wire.wire("w1", ("p0", "p1"), style: "direct")
 wire.wire("w2", ("p2", "p3"), style: "zigzag")
 wire.wire("w3", ("p4", "p5"), style: "dodge",
           dodge-y: -0.5, dodge-margins: (0.5, 0.5))
+wire.wire("w4", ("p6","p7"), style: "guided",
+          guided-center:(20%, 40%), guided-margins: (90%,87%),
+          guided-sides: ("north","south"))
+
 ```, vertical: true)
 
 #let stub = example(```
@@ -115,6 +119,46 @@ gates.gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
 gates.gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
 ```, vertical: true)
 
+#let iec-gate-and = example(```
+gates.iec-gate-and(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-and(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-nand = example(```
+gates.iec-gate-nand(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-nand(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-or = example(```
+gates.iec-gate-or(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-or(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-nor = example(```
+gates.iec-gate-nor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-nor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-xor = example(```
+gates.iec-gate-xor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-xor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-xnor = example(```
+gates.iec-gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-buf = example(```
+gates.iec-gate-buf(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-buf(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-not = example(```
+gates.iec-gate-not(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-not(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
 #let group = example(```
 element.group(
   id: "g1", name: "Group 1", stroke: (dash: "dashed"),
@@ -148,21 +192,3 @@ wire.wire("w2", ((0, 0), (1, -.5)),
           style: "zigzag", zigzag-ratio: 80%)
 wire.intersection("w1.zig")
 ```)
-
-#let capacitor = example(```
-electrical.capacitor(
-  x: 0, y: 0, w: 2, h: 1, id: "a",
-  scales: (100%, 80%), gap: 0.3
-)
-
-electrical.capacitor(
-  x: 4, y: -0.5, w: 1, h: 2, id: "b",
-  vertical: true, symbols: ([+], none)
-)
-```, vertical: true)
-
-#let resistor = example(```
-electrical.resistor(x: 0, y: 0, w: 2, h: 0.5, id: "a", zigzags: 8)
-electrical.resistor(x: 4, y: -0.5, w: 0.5, h: 2, id: "b", vertical: true)
-electrical.resistor(x: 6.5, y: 0, w: 2, h: 0.5, id: "c", zigzags: none)
-```, vertical: true)

gallery.bash

@@ -1,40 +0,0 @@
-#!/bin/bash
-
-PDFS=false
-
-while getopts "p" flag
-do
-    case "${flag}" in
-        p) PDFS=true;;
-    esac
-done
-
-echo "Generating gallery images"
-
-set -- ./gallery/*.typ
-cnt="$#"
-i=1
-for f
-do
-    f2="${f%.typ}.png"
-    echo "($i/$cnt) $f -> $f2"
-    typst c --root ./ "$f" "$f2"
-    i=$((i+1))
-done
-
-if [ "$PDFS" = true ]
-then
-    echo
-    echo "Generating gallery PDFs"
-
-    set -- ./gallery/*.typ
-    cnt="$#"
-    i=1
-    for f
-    do
-        f2="${f%.typ}.pdf"
-        echo "($i/$cnt) $f -> $f2"
-        typst c --root ./ "$f" "$f2"
-        i=$((i+1))
-    done
-fi

gallery/test3.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "../src/lib.typ": circuit, element, util, wire
 
 #set page(width: auto, height: auto, margin: .5cm)
@@ -81,57 +81,4 @@
   element.gate-xnor(
     x: 9, y: -6, w: 2, h: 2, id: "xnor"
   )
-
-  element.resistor(
-    x: 0, y: -8, w: 2, h: 0.5, id: "res1"
-  )
-
-  element.capacitor(
-    x: 3, y: (from: "res1-port-1", to: "0"),
-    w: 2, h: 0.6,
-    id: "cap1",
-    scales: (100%, 80%),
-    symbols: ([+], [-])
-  )
-
-  element.resistor(
-    x: (rel: 1, to: "cap1-port-1"),
-    y: (from: "cap1-port-1", to: "0"),
-    w: 0.5, h: 2,
-    id: "res2",
-    vertical: true,
-    zigzags: 8
-  )
-
-  element.capacitor(
-    x: (rel: 1, to: "res2.east"),
-    y: (from: "res2-port-1", to: "1"),
-    w: 0.5, h: 2,
-    id: "cap2",
-    vertical: true,
-    symbols: ([a], [b])
-  )
-
-  element.resistor(
-    x: (rel: 1, to: "cap2-port-0"),
-    y: (from: "cap2-port-0", to: "0"),
-    w: 2, h: 0.5,
-    id: "res3",
-    zigzags: none
-  )
-
-  element.resistor(
-    x: (rel: 1, to: "res3-port-1"),
-    y: (from: "res3-port-1", to: "0"),
-    w: 0.5, h: 2,
-    id: "res4",
-    zigzags: none,
-    vertical: true
-  )
-
-  wire.wire("w4", ("res1-port-1", "cap1-port-0"))
-  wire.wire("w5", ("cap1-port-1", "res2-port-0"))
-  wire.wire("w6", ("res2-port-1", "cap2-port-1"))
-  wire.wire("w7", ("cap2-port-0", "res3-port-0"))
-  wire.wire("w8", ("res3-port-1", "res4-port-0"))
 })

gallery/test4.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "../src/lib.typ": *
 
 #set page(width: auto, height: auto, margin: .5cm)

gallery/test5.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "../src/lib.typ": *
 
 #set page(width: auto, height: auto, margin: .5cm)

gallery/test6.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw, vector
+#import "@preview/cetz:0.3.2": draw, vector
 #import "../src/lib.typ": *
 
 #set page(width: auto, height: auto, margin: .5cm)

gallery/test7.typ

@@ -0,0 +1,98 @@
+#import "@preview/cetz:0.3.2": draw
+#import "../src/lib.typ": circuit, element, util, wire
+
+#set page(width: auto, height: auto, margin: .5cm)
+
+#circuit({
+  element.iec-gate-buf(
+    x: 0,
+    y: 0,
+    w: 2,
+    h: 2,
+    id: "iec-buf",
+    inputs: 1,
+  )
+  wire.stub("iec-buf-port-in0", "west")
+
+  element.iec-gate-not(
+    x: 3,
+    y: 0,
+    w: 2,
+    h: 2,
+    id: "iec-not",
+    inputs: 1,
+  )
+  wire.stub("iec-not-port-in0", "west")
+
+  element.iec-gate-and(
+    id: "iec-and",
+    x: 0,
+    y: -3,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-and-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-nand(
+    id: "iec-nand",
+    x: 3,
+    y: -3,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-nand-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-or(
+    id: "iec-or",
+    x: 0,
+    y: -6,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-or-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-nor(
+    id: "iec-nor",
+    x: 3,
+    y: -6,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-nor-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-xor(
+    id: "iec-xor",
+    x: 0,
+    y: -9,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-xor-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-xnor(
+    id: "iec-nxor",
+    x: 3,
+    y: -9,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-nxor-port-in" + str(i), "west")
+  }
+})

justfile

@@ -0,0 +1,11 @@
+# Local Variables:
+# mode: makefile
+# End:
+gallery_dir := "./gallery"
+set shell := ["bash", "-uc"]
+
+manual:
+  typst c manual.typ manual.pdf
+
+gallery:
+  for f in "{{gallery_dir}}"/*.typ; do typst c --root . "$f" "${f%typ}png"; done

manual.typ

@@ -1,10 +1,9 @@
-#import "@preview/tidy:0.3.0"
-#import "@preview/cetz:0.2.2": draw, canvas
+#import "@preview/tidy:0.4.1"
+#import "@preview/cetz:0.3.2": draw, canvas
 #import "src/lib.typ"
 #import "doc/examples.typ"
 #import "src/circuit.typ": circuit
 #import "src/element.typ"
-#import "src/electrical.typ"
 #import "src/gates.typ"
 #import "src/util.typ"
 #import "src/wire.typ"
@@ -13,7 +12,7 @@
   numbering("1.1", ..num)
 })
 #{
-  outline(indent: true, depth: 3)
+  outline(indent: auto, depth: 3)
 }
 
 #show link: set text(blue)
@@ -48,7 +47,7 @@
 
 #set page(numbering: "1/1", header: align(right)[circuiteria #sym.dash.em v#lib.version])
 #set page(
-  header: locate(loc => {
+  header: context {
     let txt = [circuiteria #sym.dash.em v#lib.version]
     let cnt = counter(heading)
     let cnt-val = cnt.get()
@@ -66,8 +65,8 @@
         #rect(width: 100%, height: .5em, radius: .25em, stroke: none, fill: util.colors.values().at(i))
       ]
     )
-  }),
-  footer: locate(loc => {
+  },
+  footer: context {
     let cnt = counter(heading)
     let cnt-val = cnt.get()
     if cnt-val.len() < 2 { return }
@@ -81,12 +80,12 @@
       ],
       counter(page).display("1/1", both: true)
     )
-  })
+  }
 )
 
 #let doc-ref(target, full: false, var: false) = {
   let (module, func) = target.split(".")
-  let label-name = module + func
+  let label-name = module + "-" + func
   let display-name = func
   if full {
     display-name = target
@@ -95,7 +94,7 @@
     label-name += "()"
     display-name += "()"
   }
-  link(label(label-name))[#display-name]
+  link(label(label-name), raw(display-name))
 }
 
 = Introduction
@@ -104,11 +103,21 @@ This package provides a way to make beautiful block circuit diagrams using the C
 
 = Usage
 
-Simply import #link("src/lib.typ") and call the `circuit` function:
+Simply import Circuiteria and call the `circuit` function:
 #pad(left: 1em)[```typ
-#import "src/lib.typ"
-#lib.circuit({
-  import lib: *
+#import "@preview/circuiteria:0.2.0"
+#circuiteria.circuit({
+  import circuiteria: *
+  ...
+})
+```]
+
+== Project installation
+If you have installed Circuiteria directly in your project, import #link("src/lib.typ") and call the `circuit` function:
+#pad(left: 1em)[```typ
+#import "src/lib.typ" as circuiteria
+#circuiteria.circuit({
+  import circuiteria: *
   ...
 })
 ```]
@@ -118,6 +127,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
 #let circuit-docs = tidy.parse-module(
   read("src/circuit.typ"),
   name: "circuit",
+  old-syntax: true,
   require-all-parameters: true
 )
 #tidy.show-module(circuit-docs)
@@ -127,6 +137,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
 #let util-docs = tidy.parse-module(
   read("src/util.typ"),
   name: "util",
+  old-syntax: true,
   require-all-parameters: true,
   scope: (
     util: util,
@@ -141,6 +152,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
 #let wire-docs = tidy.parse-module(
   read("src/wire.typ"),
   name: "wire",
+  old-syntax: true,
   require-all-parameters: true,
   scope: (
     wire: wire,
@@ -162,6 +174,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
   read("src/elements/multiplexer.typ") + "\n" +
   read("src/elements/group.typ"),
   name: "element",
+  old-syntax: true,
   scope: (
     element: element,
     circuit: circuit,
@@ -182,8 +195,14 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
   read("src/elements/logic/and.typ") + "\n" +
   read("src/elements/logic/buf.typ") + "\n" +
   read("src/elements/logic/or.typ") + "\n" +
-  read("src/elements/logic/xor.typ"),
+  read("src/elements/logic/xor.typ") + "\n" +
+  read("src/elements/logic/iec_gate.typ") + "\n" +
+  read("src/elements/logic/iec_and.typ") + "\n" +
+  read("src/elements/logic/iec_buf.typ") + "\n" +
+  read("src/elements/logic/iec_or.typ") + "\n" +
+  read("src/elements/logic/iec_xor.typ"),
   name: "gates",
+  old-syntax: true,
   scope: (
     element: element,
     circuit: circuit,
@@ -197,23 +216,3 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
 )
 
 #tidy.show-module(gates-docs, sort-functions: false)
-
-#pagebreak()
-
-#let electrical-docs = tidy.parse-module(
-  read("src/elements/electrical/capacitor.typ") + "\n" +
-  read("src/elements/electrical/resistor.typ") + "\n",
-  name: "electrical",
-  scope: (
-    element: element,
-    circuit: circuit,
-    electrical: electrical,
-    draw: draw,
-    wire: wire,
-    tidy: tidy,
-    examples: examples,
-    doc-ref: doc-ref
-  )
-)
-
-#tidy.show-module(electrical-docs, sort-functions: false)

src/circuit.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": canvas
+#import "@preview/cetz:0.3.2": canvas
 #import "@preview/tidy:0.3.0"
 
 /// Draws a block circuit diagram
@@ -9,6 +9,5 @@
 /// - length (length, ratio): Optional base unit
 /// -> none
 #let circuit(body, length: 2em) = {
-  set text(font: "Source Sans 3")
   canvas(length: length, body)
 }

src/electrical.typ

@@ -1,2 +0,0 @@
-#import "elements/electrical/capacitor.typ": capacitor
-#import "elements/electrical/resistor.typ": resistor

src/element.typ

@@ -11,8 +11,10 @@
 #import "elements/logic/or.typ": gate-or, gate-nor
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
 #import "elements/logic/buf.typ": gate-buf, gate-not
-
-#import "elements/electrical/resistor.typ": resistor
-#import "elements/electrical/capacitor.typ": capacitor
+#import "elements/logic/iec_gate.typ": iec-gate
+#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
+#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
+#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
+#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor
 
 #import "elements/group.typ": group

src/elements/alu.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "element.typ"
 #import "ports.typ": add-port
 

src/elements/block.typ

@@ -1,9 +1,9 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "element.typ"
 
-#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
+#let draw-shape(id, tl, tr, br, bl, fill, stroke, radius: 0.5em) = {
   let f = draw.rect(
-    radius: 0.5em,
+    radius: radius,
     inset: 0.5em,
     fill: fill,
     stroke: stroke,
@@ -27,13 +27,14 @@
   ports: (),
   ports-margins: (),
   fill: none,
+  radius: 0.5em,
   stroke: black + 1pt,
   id: "",
   debug: (
     ports: false
   )
 ) = element.elmt(
-  draw-shape: draw-shape,
+  draw-shape: draw-shape.with(radius: radius),
   x: x,
   y: y,
   w: w,

src/elements/electrical/capacitor.typ

@@ -1,138 +0,0 @@
-#import "@preview/cetz:0.2.2": draw
-#import "../element.typ"
-#import "../ports.typ": add-port
-
-#let draw-shape(
-  id, tl, tr, br, bl,
-  fill, stroke,
-  vertical: false,
-  gap: 0.2,
-  scales: (100%, 100%),
-  symbols: (none, none)
-) = {
-  let (x0, y0) = tl
-  let (x1, y1) = br
-
-  let w = x1 - x0
-  let h = y1 - y0
-
-  let (o0, s0) = if vertical {(y0, h)} else {(x0, w)}
-  let (o1, s1) = if vertical {(x0, w)} else {(y0, h)}
-  let m1 = o1 + s1 / 2
-
-  let pt(i, j) = if vertical {
-    (j, i)
-  } else {
-    (i, j)
-  }
-
-  let size0 = s1 * scales.first() / 100%
-  let size1 = s1 * scales.last() / 100%
-
-  if type(gap) == ratio {
-    gap = gap / 100%
-  } else {
-    gap = gap / calc.abs(s0)
-  }
-  let r0 = 0.5 - gap / 2
-  let r1 = 0.5 + gap / 2
-
-  // Coordinates in (main axis, secondary axis) format
-  let p0 = pt(o0, m1)
-  let p1 = pt(o0 + r0 * s0, m1)
-  let p2 = pt(o0 + r1 * s0, m1)
-  let p3 = pt(o0 + s0, m1)
-  
-  let p4 = pt(o0 + r0 * s0, m1 - size0 / 2)
-  let p5 = pt(o0 + r0 * s0, m1 + size0 / 2)
-  
-  let p6 = pt(o0 + r1 * s0, m1 - size1 / 2)
-  let p7 = pt(o0 + r1 * s0, m1 + size1 / 2)
-
-  let line = draw.line.with(stroke: stroke)
-  let f = draw.group(name: id, {
-    line(p0, p1)
-    line(p2, p3)
-    line(p4, p5)
-    line(p6, p7)
-
-    if symbols.first() != none {
-      draw.content(
-        p1,
-        symbols.first(),
-        anchor: if vertical {"south-west"} else {"south-east"},
-        padding: 2pt
-      )
-    }
-
-    if symbols.last() != none {
-      draw.content(
-        p2,
-        symbols.last(),
-        anchor: if vertical {"north-west"} else {"south-west"},
-        padding: 2pt
-      )
-    }
-  })
-
-  return (f, tl, tr, br, bl)
-}
-
-/// Draws a capacitor
-///
-/// #examples.capacitor
-/// For other parameters description, see #doc-ref("element.elmt")
-/// - vertical (bool): Whether the element is vertical or horizontal.
-///   - If false, port 0 is placed on the west side and port 1 on the east.\
-///   - If true, they are on the north, respectively the south sides
-/// - gap (number, ratio): The gap between both sides
-///   - if it is a number (int or float), it is interpreted as an absolute canvas-unit length
-///   - if it is a ratio, it is interpreted as proportional to the capacitor's length (width if horizontal, height if vertical)
-/// - scales (array): A pair of ratios, the sizes of the sides relative to the capacitor's height (width if vertical).
-/// - symbols (array): A pair of content or strings (or none values) to attach on the sides of the capacitor
-#let capacitor(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  name: none,
-  name-anchor: "center",
-  vertical: false,
-  gap: 0.2,
-  scales: (100%, 100%),
-  symbols: (none, none),
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  debug: (
-    ports: false
-  )
-) = {
-  let ports = if vertical {(
-    north: ((id: "0"),),
-    south: ((id: "1"),)
-  )} else {(
-    west: ((id: "0"),),
-    east: ((id: "1"),)
-  )}
-  
-  element.elmt(
-    draw-shape: draw-shape.with(
-      vertical: vertical,
-      gap: gap,
-      scales: scales,
-      symbols: symbols
-    ),
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    name: name,
-    name-anchor: name-anchor,
-    ports: ports,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    debug: debug
-  )
-}

src/elements/electrical/resistor.typ

@@ -1,106 +0,0 @@
-#import "@preview/cetz:0.2.2": draw
-#import "../element.typ"
-#import "../ports.typ": add-port
-
-#let draw-shape(
-  id, tl, tr, br, bl,
-  fill, stroke,
-  zigzags: 6,
-  vertical: false
-) = {
-  let (x0, y0) = tl
-  let (x1, y1) = br
-
-  let w = x1 - x0
-  let h = y1 - y0
-
-  let (o0, s0) = if vertical {(y0, h)} else {(x0, w)}
-  let (o1, s1) = if vertical {(x0, w)} else {(y0, h)}
-  let m1 = o1 + s1 / 2
-
-  let pt(i, j) = if vertical {
-    (j, i)
-  } else {
-    (i, j)
-  }
-
-  let p0 = pt(o0, m1)
-  let p1 = pt(o0 + 0.2 * s0, m1)
-  let p2 = pt(o0 + 0.8 * s0, m1)
-  let p3 = pt(o0 + s0, m1)
-
-  if zigzags == none {
-    let p4 = pt(o0 + 0.2 * s0, o1)
-    let p5 = pt(o0 + 0.8 * s0, o1 + s1)
-    let f = draw.group(name: id, {
-      draw.line(p0, p1)
-      draw.line(p2, p3)
-      draw.rect(p4, p5, stroke: stroke, fill: fill)
-    })
-    return (f, tl, tr, br, bl)
-  }
-  
-  let pts = (p0, p1)
-  
-  for i in range(zigzags) {
-    let r = ((i+0.5) / zigzags * 0.6 + 0.2)
-    let pos = pt(o0 + r * s0, o1 + s1 * calc.rem(i, 2))
-    pts.push(pos)
-  }
-
-  pts += (p2, p3)
-
-  let f = draw.group(name: id, {
-    draw.line(..pts, stroke: stroke)
-  })
-  return (f, tl, tr, br, bl)
-}
-
-/// Draws a resistor
-///
-/// #examples.resistor
-/// For other parameters description, see #doc-ref("element.elmt")
-/// - vertical (bool): Whether the element is vertical or horizontal. If false, port 0 is placed on the west side and port 1 on the east. If true, they are on the north, respectively the south sides
-/// - zigzags (number, none): Number of zigzags to draw. If none, a rectangle is drawn
-#let resistor(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  name: none,
-  name-anchor: "center",
-  vertical: false,
-  zigzags: 6,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  debug: (
-    ports: false
-  )
-) = {
-  let ports = if vertical {(
-    north: ((id: "0"),),
-    south: ((id: "1"),)
-  )} else {(
-    west: ((id: "0"),),
-    east: ((id: "1"),)
-  )}
-
-  element.elmt(
-    draw-shape: draw-shape.with(
-      vertical: vertical,
-      zigzags: zigzags
-    ),
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    name: name,
-    name-anchor: name-anchor,
-    ports: ports,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    debug: debug
-  )
-}

src/elements/element.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw, coordinate
+#import "@preview/cetz:0.3.2": draw, coordinate
 #import "ports.typ": add-ports, add-port
 #import "../util.typ"
 

src/elements/extender.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "element.typ"
 #import "ports.typ": add-port
 

src/elements/group.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw, coordinate
+#import "@preview/cetz:0.3.2": draw, coordinate
 #import "../util.typ"
 
 /// Draws a group of elements

src/elements/logic/and.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "gate.typ"
 
 #let draw-shape(id, tl, tr, br, bl, fill, stroke) = {

src/elements/logic/buf.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "gate.typ"
 
 #let draw-shape(id, tl, tr, br, bl, fill, stroke) = {

src/elements/logic/gate.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw, coordinate
+#import "@preview/cetz:0.3.2": draw, coordinate
 #import "../ports.typ": add-ports, add-port
 #import "../element.typ"
 

src/elements/logic/iec_and.typ

@@ -0,0 +1,70 @@
+#import "@preview/cetz:0.3.2": draw
+// #import "iec_gate.typ" as iec-gate
+#import "iec_gate.typ" as iec-gate
+
+
+/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-and
+#let iec-gate-and(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  ),
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $amp$,
+  )
+
+}
+
+/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-nand
+#let iec-gate-nand(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  ),
+) = {
+  iec-gate-and(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug,
+  )
+}

src/elements/logic/iec_buf.typ

@@ -0,0 +1,68 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+
+/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
+///
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-buf
+#let iec-gate-buf(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false,
+  ),
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: "1",
+  )
+}
+
+/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-not
+#let iec-gate-not(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false,
+  ),
+) = {
+  iec-gate-buf(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" { inverted + ("out",) } else { inverted },
+    debug: debug,
+  )
+}

src/elements/logic/iec_gate.typ

@@ -0,0 +1,125 @@
+#import "@preview/cetz:0.3.2": draw, coordinate
+#import "../ports.typ": add-ports, add-port
+#import "../element.typ"
+
+#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
+  let shapes = draw.rect(
+    inset: 0.5em,
+    fill: fill,
+    stroke: stroke,
+    name: id,
+    bl, tr
+  )
+  shapes += draw.content(
+    id + ".center",
+    [*$ symbol $*]
+  )
+  return (shapes, tl, tr, br, bl)
+}
+
+/// Draws a logic gate. This function is also available as `element.iec-gate()`
+///
+/// - draw-shape (function): see #doc-ref("element.elmt")
+/// - x (number, dictionary): see #doc-ref("element.elmt")
+/// - y (number, dictionary): see #doc-ref("element.elmt")
+/// - w (number): see #doc-ref("element.elmt")
+/// - h (number): see #doc-ref("element.elmt")
+/// - inputs (int): The number of inputs
+/// - fill (none, color): see #doc-ref("element.elmt")
+/// - stroke (stroke): see #doc-ref("element.elmt")
+/// - id (str): see #doc-ref("element.elmt")
+/// - inverted (str, array): Either "all" or an array of port ids to display as inverted
+/// - inverted-radius (number): The radius of inverted ports dot
+/// - debug (dictionary): see #doc-ref("element.elmt")
+/// - symbol (str): The symbol to display at the center of the gate
+#let iec-gate(
+  draw-shape: default-draw-shape,
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  inverted-radius: 0.1,
+  debug: (
+    ports: false
+  ),
+  symbol: "",
+) = draw.get-ctx(ctx => {
+  let width = w
+  let height = h
+
+  let x = x
+  let y = y
+  if x == none { panic("Parameter x must be set") }
+  if y == none { panic("Parameter y must be set") }
+  if w == none { panic("Parameter w must be set") }
+  if h == none { panic("Parameter h must be set") }
+
+  if (type(x) == dictionary) {
+    let offset = x.rel
+    let to = x.to
+    let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to))
+    x = to-pos.at(0)
+  }
+  
+  if (type(y) == dictionary) {
+    let from = y.from
+    let to = y.to
+    
+    let dy
+    if to == "out" {
+      dy = height / 2
+    } else {
+      dy = height * (i + 0.5) / inputs
+    }
+    
+    let (ctx, from-pos) = coordinate.resolve(ctx, from)
+    y = from-pos.at(1) + dy - height
+  }
+
+  let tl = (x, y + height)
+  let tr = (x + width, y + height)
+  let br = (x + width, y)
+  let bl = (x, y)
+
+  // Workaround because CeTZ needs to have all draw functions in the body
+  let func = {}
+  (func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol)
+  func
+
+  let space = 100% / inputs
+  for i in range(inputs) {
+    let pct = (i + 0.5) * space
+    let port-pos = (tl, pct, bl)
+    let port-name = "in" + str(i)
+    if inverted == "all" or port-name in inverted {
+      draw.circle(
+        port-pos,
+        radius: inverted-radius,
+        anchor: "east",
+        stroke: stroke
+      )
+      port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
+    }
+    add-port(
+      id, "west",
+      (id: port-name), port-pos,
+      debug: debug.ports
+    )
+  }
+
+  let out-pos = id + ".east"
+  if inverted == "all" or "out" in inverted {
+    draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke)
+    out-pos = (rel: (2 * inverted-radius, 0), to: out-pos)
+  }
+  add-port(
+    id, "east",
+    (id: "out"), out-pos,
+    debug: debug.ports
+  )
+})

src/elements/logic/iec_or.typ

@@ -0,0 +1,67 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-or
+#let iec-gate-or(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $>= 1$,
+  )
+}
+
+/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-nor
+#let iec-gate-nor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate-or(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug
+  )
+}

src/elements/logic/iec_xor.typ

@@ -0,0 +1,67 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-xor
+#let iec-gate-xor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $= 1$,
+  )
+}
+
+/// Draws an IEC-XNOR gate. This function is also available as `element.iec-gate-xnor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-xnor
+#let iec-gate-xnor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate-xor(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug
+  )
+}

src/elements/logic/or.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "gate.typ"
 
 #let draw-shape(id, tl, tr, br, bl, fill, stroke) = {

src/elements/logic/xor.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "gate.typ"
 
 #let space = 10%

src/elements/multiplexer.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "../util.typ"
 #import "element.typ"
 #import "ports.typ": add-port

src/elements/ports.typ

@@ -1,4 +1,4 @@
-#import "@preview/cetz:0.2.2": draw
+#import "@preview/cetz:0.3.2": draw
 #import "../util.typ": rotate-anchor
 
 #let add-port(

src/gates.typ

@@ -3,3 +3,8 @@
 #import "elements/logic/or.typ": gate-or, gate-nor
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
 #import "elements/logic/buf.typ": gate-buf, gate-not
+#import "elements/logic/iec_gate.typ": iec-gate
+#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
+#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
+#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
+#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor

src/lib.typ

@@ -1,7 +1,6 @@
-#let version = version(0, 1, 0)
+#let version = version(0, 2, 0)
 
 #import "circuit.typ": circuit
-#import "electrical.typ"
 #import "element.typ"
 #import "gates.typ"
 #import "util.typ"

src/wire.typ

@@ -1,9 +1,9 @@
-#import "@preview/cetz:0.2.2": draw, coordinate
+#import "@preview/cetz:0.3.2": draw, coordinate
 #import "util.typ": opposite-anchor
 
 /// List of valid wire styles
 /// #examples.wires
-#let wire-styles = ("direct", "zigzag", "dodge")
+#let wire-styles = ("direct", "zigzag", "dodge", "guided")
 #let signal-width = 1pt
 #let bus-width = 1.5pt
 
@@ -109,6 +109,88 @@
   return (points, anchors)
 }
 
+#let get-guided-wire(pts, margins, sides, center-guides, ctx) = {
+  let start = pts.first()
+  let end = pts.last()
+  let (margin-start, margin-end) = margins
+  let (side-start, side-end) = sides
+  let (center_horizontal, center_vertical) = center-guides
+
+  let (ctx, p0) = coordinate.resolve(ctx, start)
+  let (ctx, p6) = coordinate.resolve(ctx, end)
+  p0 = (x: p0.first(), y: p0.at(1))
+  p6 = (x: p6.first(), y: p6.at(1))
+
+  let box_width = calc.abs(p6.x - p0.x)
+  let box_height = calc.abs(p6.y - p0.y)
+
+  // finding correct dx and dy
+  let dx1 = box_width * margin-start / 100%
+  if side-start == "west" {
+    dx1 *= -1
+  } else if side-start == "north" or side-start == "south" { dx1 = 0}
+
+  let dx2 = box_width * margin-end / 100%
+  if side-end == "west" {
+    dx2 *= -1
+  } else if side-end == "north" or side-end == "south" { dx2 = 0}
+
+  let dy1 = box_height * margin-start / 100%
+  if side-start == "south" {
+    dy1 *= -1
+  } else if side-start == "west" or side-start == "east" { dy1 = 0}
+
+  let dy2 = box_height * margin-end / 100%
+  if side-end == "south" {
+    dy2 *= -1
+  } else if side-end == "west" or side-end == "east" { dy2 = 0}
+
+
+  // points that are closest to the edge points
+  let p1 = (p0.x + dx1, p0.y + dy1)
+  let p5 = (p6.x + dx2, p6.y + dy2)
+
+
+  // middle point
+  let center_x = p0.x + box_width * center_horizontal / 100%
+  let center_y = p0.y + box_height * center_vertical / 100%
+  let p3 = (center_x, center_y)
+
+  // setting up the points for that touch the guides
+  let p2 = (0,0)
+  let p4 = (0,0)
+  if side-start in ("north", "south") {
+    p2 = (horizontal: p3, vertical: p1)
+  } else {
+    p2 = (horizontal: p1, vertical: p3)
+  }
+  if side-end in ("north", "south") {
+    p4 = (horizontal: p3, vertical: p5)
+  } else if side-end in ("east", "west") {
+    p4 = (horizontal: p5, vertical: p3)
+  }
+
+  // returning
+  let points = (
+    start,
+    p1,
+    p2,
+    p3,
+    p4,
+    p5,
+    end
+  )
+  let anchors = (
+    "start": start,
+    "start2": points.at(1),
+    "guide-start": points.at(2),
+    "center": points.at(3),
+    "guide-end": points.at(4),
+    "end2": points.at(5),
+    "end": end
+  )
+  return (points, anchors)
+}
 /// Draws a wire between two points
 /// - id (str): The wire's id, for future reference (anchors)
 /// - pts (array): The two points (as CeTZ compatible coordinates, i.e. XY, relative positions, ids, etc.)
@@ -127,6 +209,9 @@
 /// - dodge-y (number): Y position to dodge the wire to (only with style "dodge")
 /// - dodge-sides (array): The start and end sides (going out of the connected element) of the wire (only with style "dodge")
 /// - dodge-margins (array): The start and end margins (i.e. space before dodging) of the wire (only with style "dodge")
+/// - guided-center (array): the horizontal and vertical guides of the center guides (only with style "guided")
+/// - guided-margins (array): the start and end of guided margins of the wire (only with style "guided")
+/// - guided-sides (array): the side of start and end array (must be either "north", "south", "west", "east") (only work with style "guided")
 #let wire(
   id, pts,
   bus: false,
@@ -137,6 +222,9 @@
   dashed: false,
   style: "direct",
   reverse: false,
+  guided-center: (50%, 50%),
+  guided-margins: (5%, 5%),
+  guided-sides: ("east", "west"),
   directed: false,
   rotate-name: true,
   zigzag-ratio: 50%,
@@ -178,6 +266,14 @@
       dodge-sides,
       ctx
     )
+  } else if style == "guided" {
+    (points, anchors) = get-guided-wire(
+      pts,
+      guided-margins,
+      guided-sides,
+      guided-center,
+      ctx
+    )
   }
 
   let mark = (fill: color)

typst.toml

@@ -1,7 +1,7 @@
 [package]
 name = "circuiteria"
-version = "0.1.0"
-compiler = "0.11.0"
+version = "0.2.0"
+compiler = "0.13.0"
 repository = "https://git.kb28.ch/HEL/circuiteria"
 entrypoint = "src/lib.typ"
 authors = [
@@ -11,4 +11,4 @@ categories = [ "visualization" ]
 license = "Apache-2.0"
 description = "Drawing block circuits with Typst made easy, using CeTZ"
 keywords = [ "circuit", "block", "draw" ]
-exclude = [ "gallery", "gallery.bash", "doc" ]
+exclude = [ "gallery", "justfile", "doc" ]